soc/amd/picasso: Convert BERT reserved region from cbmem

Picasso's BERT region should not have been moved to cbmem in commit
  901cb9c "soc/amd/picasso: Move BERT region to cbmem".  This
causes an error of "APEI: Can not request [] for APEI BERT registers.

FSP has been modified to set aside a requested region size for BERT,
simiar to TSEG.  Remove the cbmem reservation and locate the region
by searching for the HOB.

BUG=b:136987699
TEST=Check that BERT is allocated

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/picasso/mca.c

@@ -193,31 +193,3 @@ void check_mca(void)
 	for (i = 0 ; i < num_banks ; i++)
 		wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts);
 }
-
-void bert_reserved_region(void **start, size_t *size)
-{
-	const struct cbmem_entry *bert;
-
-	*start = NULL;
-	*size = 0;
-
-	bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA);
-	if (!bert)
-		return;
-
-	*start = cbmem_entry_start(bert);
-	*size = cbmem_entry_size(bert);
-}
-
-static void alloc_bert_in_cbmem(int unused)
-{
-	void *p;
-
-	if (CONFIG(ACPI_BERT)) {
-		p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, CONFIG_ACPI_BERT_SIZE);
-		if (!p)
-			printk(BIOS_ERR, "Error: BERT region was not added\n");
-	}
-}
-
-ROMSTAGE_CBMEM_INIT_HOOK(alloc_bert_in_cbmem)

src/soc/amd/picasso/memmap.c

@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
+#include <arch/bert_storage.h>
 #include <memrange.h>
 #include <fsp/util.h>
 #include <FspGuids.h>
@@ -60,6 +61,25 @@ void smm_region(uintptr_t *start, size_t *size)
 	}
 }
 
+void bert_reserved_region(void **start, size_t *size)
+{
+	struct range_entry bert;
+	int status;
+
+	*start = NULL;
+	*size = 0;
+
+	status = fsp_find_range_hob(&bert, AMD_FSP_BERT_HOB_GUID.b);
+
+	if (status < 0) {
+		printk(BIOS_ERR, "Error: unable to find BERT HOB\n");
+		return;
+	}
+
+	*start = (void *)(uintptr_t)range_entry_base(&bert);
+	*size = range_entry_size(&bert);
+}
+
 void memmap_stash_early_dram_usage(void)
 {
 	struct memmap_early_dram *e;

src/soc/amd/picasso/romstage.c

@@ -32,6 +32,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
 	mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
+	mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
 	mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
 	mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;