jasperlake: enable DPTF functionality for dedede
Enable DPTF functionality on jasperlake based dedede platform BRANCH=None BUG=None TEST=Built for dedede system Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -55,4 +55,13 @@ DefinitionBlock(
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/* ACPI code for EC functions */
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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}
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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}
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}
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@ -144,6 +144,17 @@ chip soc/intel/jasperlake
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# Enable Speed Shift Technology support
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# Enable Speed Shift Technology support
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register "speed_shift_enable" = "1"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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register "power_limits_config" = "{
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.tdp_pl1_override = 6,
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.tdp_pl2_override = 20,
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}"
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# Enable processor thermal control
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register "Device4Enable" = "1"
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# chipset_lockdown configuration
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# chipset_lockdown configuration
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# Use below format to override value in overridetree.cb if required
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# Use below format to override value in overridetree.cb if required
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# format:
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# format:
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@ -153,7 +164,7 @@ chip soc/intel/jasperlake
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device domain 0 on
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 off end # SA Thermal device
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device pci 04.0 on end # SA Thermal device
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device pci 05.0 off end # IPU
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device pci 05.0 off end # IPU
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device pci 09.0 off end # Intel Trace Hub
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device pci 09.0 off end # Intel Trace Hub
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device pci 12.6 off end # GSPI 2
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device pci 12.6 off end # GSPI 2
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@ -0,0 +1,48 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Below values might change after Thermal Tuning. */
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#define DPTF_CPU_PASSIVE 90
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#define DPTF_CPU_CRITICAL 99
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Memory"
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#define DPTF_TSR0_PASSIVE 80
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#define DPTF_TSR0_CRITICAL 90
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "Ambient"
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#define DPTF_TSR1_PASSIVE 55
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#define DPTF_TSR1_CRITICAL 80
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 0 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 1 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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3000, /* PowerLimitMinimum */
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6000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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6000, /* PowerLimitMinimum */
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20000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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