soc/intel/quark: Add legacy SPI flash controller driver
Add SPI driver code for the legacy SPI flash controller. Enable erase and write support allowing coreboot to save non-volatile data into the SPI flash. TEST=Build and run on Galileo Gen2. Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
parent
0cae6e9e5d
commit
d9351099ef
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@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_RESET
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select SOC_SETS_MSRS
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select SPI_FLASH
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select TSC_CONSTANT_RATE
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select UART_OVERRIDE_REFCLK
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select UDELAY_TSC
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@ -58,6 +58,8 @@ ramstage-y += northcluster.c
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ramstage-y += reg_access.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += sd.c
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ramstage-y += spi.c
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ramstage-y += spi_debug.c
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ramstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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@ -28,6 +28,7 @@
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#define I2CGPIO_DEVID 0x0934
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#define HSUART_DEVID 0x0936
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#define EHCI_DEVID 0x0939
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#define LPC_DEVID 0X095E
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#define PCIE_PORT0_DEVID 0x11c3
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#define PCIE_PORT1_DEVID 0x11c4
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@ -0,0 +1,96 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_SPI_H__
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#define __SOC_SPI_H__
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#include <spi_flash.h>
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#include <spi-generic.h>
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#define SPISTS 0x3020 /* Status register */
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#define SPICTL 0x3022 /* Control register */
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#define SPIADDR 0x3024 /* Flash chip select and 24-bit address */
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#define SPIDATA 0x3028 /* 64-byte send/receive data buffer */
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#define SPIBBAR 0x3070 /* BIOS base address */
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#define SPIPREOP 0x3074 /* Prefix opcode table */
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#define SPITYPE 0x3076 /* Opcode type table */
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#define SPIOPMENU 0x3078 /* Opcode table */
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#define SPIPBR0 0x3080 /* Protected BIOS range */
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#define SPIPBR1 0x3084
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#define SPIPBR2 0x3088
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struct flash_ctrlr {
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uint8_t rsvd_0x00[0x3020];/* 0x00 */
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uint16_t status; /* 0x3020: Status register */
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uint16_t control; /* 0x3022: Control register */
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uint32_t address; /* 0x3024: Chip select and 24-bit address */
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uint8_t data[64]; /* 0x3028: 64-byte send/receive data buffer */
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uint8_t rsvd_0x68[8]; /* 0x3068 */
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uint32_t bbar; /* 0x3070: BIOS base address */
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uint8_t prefix[2]; /* 0x3074: Prefix opcode table */
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uint16_t type; /* 0x3076: Opcode type table */
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uint8_t opmenu[8]; /* 0x3078: Opcode table */
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uint32_t pbr[3]; /* 0x3080: Protected BIOS range */
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};
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/* 0x3020: SPISTS */
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#define SPISTS_CLD 0x8000 /* Lock SPI controller configuration */
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#define SPISTS_BA 0x0008 /* Access is blocked */
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#define SPISTS_CD 0x0004 /* Cycle done */
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#define SPISTS_CIP 0x0001 /* Cycle in progress */
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/* 0x3022: SPICTL */
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#define SPICTL_SMIEN 0x8000 /* Assert SMI_B at cycle done */
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#define SPICTL_DC 0x4000 /* Cycle contains data */
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#define SPICTL_DBCNT 0x3f00 /* Data byte count - 1, 1 - 64 bytes */
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#define SPICTL_DBCNT_SHIFT 8
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#define SPICTL_COPTR 0x0070 /* Opcode menu index, 0 - 7 */
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#define SPICTL_COPTR_SHIFT 4
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#define SPICTL_SOPTR 0x0008 /* Prefix index, 0 - 1 */
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#define SPICTL_SOPTR_SHIFT 3
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#define SPICTL_ACS 0x0004 /* Atomic cycle sequence */
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#define SPICTL_CG 0x0002 /* Cycle go */
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#define SPICTL_AR 0x0001 /* Access request */
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/* 0x3076: SPITYPE */
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#define SPITYPE_ADDRESS 0x0002 /* 3-byte address required */
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#define SPITYPE_PREFIX 0x0001 /* Prefix required, write/erase cycle */
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/*
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* 0x3080: PBR0
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* 0x3084: PBR1
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* 0x3088: PBR2
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*/
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#define SPIPBR_WPE 0x80000000 /* Write protect enable */
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#define SPIPBR_PRL 0x00fff000 /* Protected range limit */
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#define SPIPBR_PRB_SHIFT 12
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#define SPIPBR_PRB 0x00000fff /* Protected range base */
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struct spi_context {
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volatile struct flash_ctrlr *ctrlr;
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uint16_t control;
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uint16_t prefix;
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};
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extern const struct spi_ctrlr spi_driver;
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void spi_bios_base(uint32_t bios_base_address);
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void spi_controller_lock(void);
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void spi_display(volatile struct flash_ctrlr *ctrlr);
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const char *spi_opcode_name(int opcode);
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int spi_protection(uint32_t address, uint32_t length);
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#endif /* __SOC_SPI_H__ */
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@ -0,0 +1,301 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <assert.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include <delay.h>
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#include <soc/pci_devs.h>
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#include <soc/QuarkNcSocId.h>
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#include <soc/spi.h>
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struct spi_context spi_driver_context = {
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NULL,
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0,
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0
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};
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void spi_bios_base(uint32_t bios_base_address)
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{
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uint32_t address;
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volatile struct flash_ctrlr *ctrlr = spi_driver_context.ctrlr;
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/* Prevent all SPI operations below this address */
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address = 0xff000000 | bios_base_address;
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ctrlr->bbar = address;
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}
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void spi_controller_lock(void)
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{
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volatile struct flash_ctrlr *ctrlr = spi_driver_context.ctrlr;
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/* Prevent BIOS and system from changing the SPI controller setup */
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ctrlr->status |= SPISTS_CLD;
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}
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int spi_protection(uint32_t address, uint32_t length)
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{
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uint32_t base;
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volatile struct flash_ctrlr *ctrlr = spi_driver_context.ctrlr;
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int index;
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uint32_t limit;
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uint32_t protect;
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uint32_t value;
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/* Determine the protection range */
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base = address;
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limit = address + length - 1;
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protect = SPIPBR_WPE | (limit & SPIPBR_PRL)
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| ((base >> SPIPBR_PRB_SHIFT) & SPIPBR_PRB);
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/* Walk the list of protected areas */
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for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) {
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value = read32(&ctrlr->pbr[index]);
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/* Don't duplicate if the range is already protected */
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if (value == protect)
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return 0;
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/* Use the first free register to protect this range */
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if ((value & SPIPBR_WPE) == 0) {
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write32(&ctrlr->pbr[index], protect);
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return 0;
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}
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}
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/* No free protection range registers */
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printk(BIOS_ERR,
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"Failed to set protection: 0x%08x - 0x%08x, PRRs full!\n",
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address, address + length - 1);
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return -1;
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}
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static int xfer(const struct spi_slave *slave, const void *dout,
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size_t bytesout, void *din, size_t bytesin)
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{
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struct spi_context *context;
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uint16_t control;
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volatile struct flash_ctrlr *ctrlr;
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uint8_t *data;
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int index;
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uint8_t opcode;
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uint32_t status;
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int type;
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/* Locate the context structure */
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context = &spi_driver_context;
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ctrlr = context->ctrlr;
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/* Validate the buffer sizes */
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if (bytesin > sizeof(ctrlr->data)) {
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printk(BIOS_ERR, "bytesin > %ld\n", sizeof(ctrlr->data));
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goto error;
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}
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if (bytesin && (din == NULL)) {
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printk(BIOS_ERR, "din is NULL\n");
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goto error;
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}
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if (bytesout == 0) {
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/* Check for a read operation */
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if (bytesin == 0) {
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printk(BIOS_ERR, "bytesout and bytesin == 0\n");
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goto error;
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}
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/* Issue the read operation */
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control = context->control;
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control |= SPICTL_DC | ((bytesin - 1) << SPICTL_DBCNT_SHIFT);
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goto start_cycle;
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}
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/* Locate the opcode in the opcode table */
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data = (uint8_t *)dout;
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opcode = *data++;
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bytesout -= 1;
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for (index = 0; index < sizeof(ctrlr->opmenu); index++)
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if (opcode == ctrlr->opmenu[index])
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break;
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/* Check for a prefix byte */
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if (index == sizeof(ctrlr->opmenu)) {
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for (index = 0; index < sizeof(ctrlr->prefix); index++)
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if (opcode == ctrlr->prefix[index])
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break;
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/* Handle the unknown opcode error */
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if (index == sizeof(ctrlr->prefix)) {
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printk(BIOS_ERR, "Unknown SPI flash opcode\n");
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goto error;
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}
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/* Save the index for the next operation */
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context->prefix = index;
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return 0;
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}
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/* Get the opcode type */
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type = (ctrlr->type >> (index * 2))
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& (SPITYPE_ADDRESS | SPITYPE_PREFIX);
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/* Determine if the opcode has an address */
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if (type & SPITYPE_ADDRESS) {
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if (bytesout < 3) {
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printk(BIOS_ERR, "Missing address bytes\n");
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goto error;
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}
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/* Use chip select 0 */
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ctrlr->address = (data[0] << 16)
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| (data[1] << 8)
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| data[2];
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status = ctrlr->address;
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data += 3;
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bytesout -= 3;
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}
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/* Build the control value */
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control = (index << SPICTL_COPTR_SHIFT)
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| (context->prefix << SPICTL_SOPTR_SHIFT)
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| SPICTL_CG | SPICTL_AR;
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if (bytesout) {
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memcpy((void *)&ctrlr->data[0], data, bytesout);
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control |= SPICTL_DC | ((bytesout - 1) << SPICTL_DBCNT_SHIFT);
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}
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/* Save the control value for the read operation request */
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if (!(type & SPITYPE_PREFIX)) {
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context->control = control;
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return 0;
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}
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/* Write operations require a prefix */
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control |= SPICTL_ACS;
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start_cycle:
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/* Start the SPI cycle */
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ctrlr->control = control;
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status = ctrlr->control;
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context->prefix = 0;
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/* Wait for the access to complete */
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while ((status = ctrlr->status) & SPISTS_CIP)
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udelay(1);
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/* Clear any errors */
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ctrlr->status = status;
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/* Handle the blocked access error */
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if (status & SPISTS_BA) {
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printk(BIOS_ERR, "SPI access blocked!\n");
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return -1;
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}
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/* Check for done */
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if (status & SPISTS_CD) {
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/* Return any receive data */
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if (bytesin)
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memcpy(din, (void *)&ctrlr->data[0], bytesin);
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return 0;
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}
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/* Handle the timeout error */
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printk(BIOS_ERR, "SPI transaction timeout!\n");
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error:
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context->prefix = 0;
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return -1;
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}
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void spi_init(void)
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{
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uint32_t bios_control;
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struct spi_context *context;
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volatile struct flash_ctrlr *ctrlr;
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device_t dev;
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uint32_t rcba;
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/* Determine the base address of the SPI flash controller */
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context = &spi_driver_context;
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dev = dev_find_device(PCI_VENDOR_ID_INTEL, LPC_DEVID, NULL);
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rcba = pci_read_config32(dev, R_QNC_LPC_RCBA);
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if (!(rcba & B_QNC_LPC_RCBA_EN)) {
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printk(BIOS_ERR, "RBCA not enabled\n");
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return;
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}
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rcba &= B_QNC_LPC_RCBA_MASK;
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ctrlr = (volatile struct flash_ctrlr *)rcba;
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/* Enable writes to the SPI flash */
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bios_control = pci_read_config32(dev, R_QNC_LPC_BIOS_CNTL);
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bios_control |= B_QNC_LPC_BIOS_CNTL_BIOSWE;
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pci_write_config32(dev, R_QNC_LPC_BIOS_CNTL, bios_control);
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/* Setup the SPI flash controller */
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context->ctrlr = ctrlr;
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ctrlr->opmenu[0] = 0x03; /* Read */
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ctrlr->opmenu[1] = 0x0b; /* Read fast */
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ctrlr->opmenu[2] = 0x05; /* Read status */
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ctrlr->opmenu[3] = 0x9f; /* Read ID */
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ctrlr->opmenu[4] = 0x02; /* Page program */
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ctrlr->opmenu[5] = 0x20; /* Erase 4 KiB */
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ctrlr->opmenu[6] = 0xd8; /* Erase 64 KiB */
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ctrlr->opmenu[7] = 0x01; /* Write status */
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ctrlr->prefix[0] = 0x50; /* Write status enable */
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ctrlr->prefix[1] = 0x06; /* Write enable */
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ctrlr->type = SPITYPE_ADDRESS /* Read */
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| (SPITYPE_ADDRESS << 2) /* Read fast */
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| (0 << 4) /* Read status */
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| (0 << 6) /* Read ID */
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| ((SPITYPE_ADDRESS | SPITYPE_PREFIX) << 8) /* Page program */
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| ((SPITYPE_ADDRESS | SPITYPE_PREFIX) << 10) /* Erase 4 KiB */
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| ((SPITYPE_ADDRESS | SPITYPE_PREFIX) << 12) /* Erase 64 KiB */
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| (SPITYPE_PREFIX << 14); /* Write status */
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}
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static void spi_init_cb(void *unused)
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{
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struct spi_flash flash;
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spi_init();
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if (spi_flash_probe(0, 0, &flash)) {
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printk(BIOS_DEBUG, "SPI flash failed initialization!\n");
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return;
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}
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printk(BIOS_DEBUG, "SPI flash successfully initialized\n");
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
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const struct spi_ctrlr spi_driver = {
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.xfer = xfer,
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.max_xfer_size = 64,
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.deduct_cmd_len = false,
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};
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const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
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{
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.ctrlr = &spi_driver,
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.bus_start = 0,
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.bus_end = 0,
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},
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};
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const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
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@ -0,0 +1,113 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation. All rights reserved.
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*
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||||
* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/spi.h>
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const char *spi_opcode_name(int opcode)
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{
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const char *op_name;
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switch (opcode) {
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default:
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op_name = "Unknown";
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break;
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case 1:
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||||
op_name = "Write Status";
|
||||
break;
|
||||
case 2:
|
||||
op_name = "Page Program";
|
||||
break;
|
||||
case 3:
|
||||
op_name = "Read Data";
|
||||
break;
|
||||
case 5:
|
||||
op_name = "Read Status";
|
||||
break;
|
||||
case 6:
|
||||
op_name = "Write Data Enable";
|
||||
break;
|
||||
case 0x0b:
|
||||
op_name = "Fast Read";
|
||||
break;
|
||||
case 0x20:
|
||||
op_name = "Erase 4 KiB";
|
||||
break;
|
||||
case 0x50:
|
||||
op_name = "Write Status Enable";
|
||||
break;
|
||||
case 0x9f:
|
||||
op_name = "Read ID";
|
||||
break;
|
||||
case 0xd8:
|
||||
op_name = "Erase 64 KiB";
|
||||
break;
|
||||
}
|
||||
return op_name;
|
||||
}
|
||||
|
||||
void spi_display(volatile struct flash_ctrlr *ctrlr)
|
||||
{
|
||||
int index;
|
||||
int opcode;
|
||||
const char *op_name;
|
||||
int prefix;
|
||||
int status;
|
||||
int type;
|
||||
|
||||
/* Display the prefixes */
|
||||
printk(BIOS_DEBUG, "Prefix Table\n");
|
||||
for (index = 0; index < 2; index++) {
|
||||
prefix = ctrlr->prefix[index];
|
||||
op_name = spi_opcode_name(prefix);
|
||||
printk(BIOS_DEBUG, " %d: 0x%02x (%s)\n", index, prefix,
|
||||
op_name);
|
||||
}
|
||||
|
||||
/* Display the opcodes */
|
||||
printk(BIOS_DEBUG, "Opcode Menu\n");
|
||||
for (index = 0; index < 8; index++) {
|
||||
opcode = ctrlr->opmenu[index];
|
||||
type = (ctrlr->type >> (index << 1)) & 3;
|
||||
op_name = spi_opcode_name(opcode);
|
||||
printk(BIOS_DEBUG, " %d: 0x%02x (%s), %s%s\n", index, opcode,
|
||||
op_name,
|
||||
(type & SPITYPE_PREFIX) ? "Write" : "Read",
|
||||
(type & SPITYPE_ADDRESS) ? ", w/3 byte address" : "");
|
||||
}
|
||||
|
||||
/* Display the BIOS base address */
|
||||
printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar);
|
||||
|
||||
/* Display the protection ranges */
|
||||
printk(BIOS_DEBUG, "BIOS Protected Range Regsiters\n");
|
||||
for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) {
|
||||
status = ctrlr->pbr[index];
|
||||
printk(BIOS_DEBUG, " %d: 0x%08x: 0x%08x - 0x%08x %s\n",
|
||||
index, status,
|
||||
0xff000000 | (0x1000000 - CONFIG_ROM_SIZE)
|
||||
| ((status & SPIPBR_PRB) << SPIPBR_PRB_SHIFT),
|
||||
0xff800fff | (0x1000000 - CONFIG_ROM_SIZE)
|
||||
| (status & SPIPBR_PRL),
|
||||
(status & SPIPBR_WPE) ? "Protected" : "Unprotected");
|
||||
}
|
||||
|
||||
/* Display locked status */
|
||||
status = ctrlr->status;
|
||||
printk(BIOS_DEBUG, "0x%04x: SPISTS, Tables %s\n", status,
|
||||
(status & SPISTS_CLD) ? "Locked" : "Unlocked");
|
||||
}
|
||||
Loading…
Reference in New Issue