soc/intel/cannonlake: Dump ME f/w version and status information
At the end of device enable, print the ME f/w version number. Before resume or loading payload, dump the ME's Host Firmware Status registers. BUG=b:131437724 BRANCH=none TEST=Prints seemingly sane values on WHL and CML devices. Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak
Patrick Georgi
parent
fa6233daeb
commit
d93531bcc8
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@ -43,6 +43,7 @@ ramstage-y += gspi.c
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ramstage-y += i2c.c
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ramstage-y += i2c.c
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ramstage-y += lockdown.c
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ramstage-y += lockdown.c
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ramstage-y += lpc.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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ramstage-y += memmap.c
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ramstage-y += memmap.c
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ramstage-y += nhlt.c
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ramstage-y += nhlt.c
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ramstage-y += p2sb.c
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ramstage-y += p2sb.c
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@ -26,6 +26,7 @@
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#include <intelblocks/tco.h>
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#include <intelblocks/tco.h>
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#include <reg_script.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <spi-generic.h>
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#include <soc/me.h>
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#include <soc/p2sb.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pcr_ids.h>
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@ -94,6 +95,8 @@ static void soc_finalize(void *unused)
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{
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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dump_me_status();
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pch_finalize();
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pch_finalize();
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CANNONLAKE_ME_H_
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#define _CANNONLAKE_ME_H_
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void dump_me_status(void);
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#endif /* _CANNONLAKE_ME_H_ */
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@ -0,0 +1,299 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Google LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <bootstate.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <intelblocks/cse.h>
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#include <soc/me.h>
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#include <soc/pci_devs.h>
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#include <stdint.h>
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#include <stdlib.h>
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/* Miscellaneous constants */
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enum {
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MKHI_GEN_GROUP_ID = 0xFF,
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MKHI_GET_FW_VERSION = 0x02,
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ME_OPMODE_NORMAL = 0x00,
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ME_WSTATE_NORMAL = 0x05,
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};
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/* HFSTS register offsets in PCI config space */
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enum {
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PCI_ME_HFSTS1 = 0x40,
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PCI_ME_HFSTS2 = 0x48,
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PCI_ME_HFSTS3 = 0x60,
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PCI_ME_HFSTS4 = 0x64,
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PCI_ME_HFSTS5 = 0x68,
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PCI_ME_HFSTS6 = 0x6C,
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};
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/* Host Firmware Status Register 1 */
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union hfsts1 {
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uint32_t raw;
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struct {
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uint32_t working_state : 4;
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uint32_t mfg_mode : 1;
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uint32_t fpt_bad : 1;
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uint32_t operation_state : 3;
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uint32_t fw_init_complete : 1;
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uint32_t ft_bup_ld_flr : 1;
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uint32_t fw_upd_in_progress : 1;
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uint32_t error_code : 4;
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uint32_t operation_mode : 4;
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uint32_t reset_count : 4;
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uint32_t boot_options : 1;
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uint32_t rsvd0 : 1;
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uint32_t bist_state : 1;
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uint32_t bist_reset_req : 1;
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uint32_t power_source : 2;
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uint32_t reserved1 : 1;
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uint32_t d0i3_support_valid : 1;
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} __packed fields;
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};
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/* Host Firmware Status Register 2 */
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union hfsts2 {
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uint32_t raw;
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struct {
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uint32_t nftp_load_failure : 1;
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uint32_t icc_prog_status : 2;
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uint32_t invoke_mebx : 1;
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uint32_t cpu_replaced : 1;
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uint32_t rsvd0 : 1;
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uint32_t mfs_failure : 1;
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uint32_t warm_reset_rqst : 1;
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uint32_t cpu_replaced_valid : 1;
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uint32_t low_power_state : 1;
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uint32_t me_power_gate : 1;
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uint32_t ipu_needed : 1;
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uint32_t forced_safe_boot : 1;
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uint32_t rsvd1 : 2;
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uint32_t listener_change : 1;
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uint32_t status_data : 8;
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uint32_t current_pmevent : 4;
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uint32_t phase : 4;
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} __packed fields;
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};
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/* Host Firmware Status Register 3 */
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union hfsts3 {
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uint32_t raw;
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};
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/* Host Firmware Status Register 4 */
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union hfsts4 {
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uint32_t raw;
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struct {
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uint32_t rsvd0 : 9;
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uint32_t enforcement_flow : 1;
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uint32_t sx_resume_type : 1;
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uint32_t rsvd1 : 1;
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uint32_t tpms_disconnected : 1;
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uint32_t rvsd2 : 1;
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uint32_t fwsts_valid : 1;
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uint32_t boot_guard_self_test : 1;
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uint32_t rsvd3 : 16;
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} __packed fields;
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};
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/* Host Firmware Status Register 5 */
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union hfsts5 {
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uint32_t raw;
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struct {
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uint32_t acm_active : 1;
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uint32_t valid : 1;
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uint32_t result_code_source : 1;
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uint32_t error_status_code : 5;
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uint32_t acm_done_sts : 1;
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uint32_t timeout_count : 7;
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uint32_t scrtm_indicator : 1;
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uint32_t inc_boot_guard_acm : 4;
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uint32_t inc_key_manifest : 4;
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uint32_t inc_boot_policy : 4;
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uint32_t rsvd0 : 2;
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uint32_t start_enforcement : 1;
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} __packed fields;
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};
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/* Host Firmware Status Register 6 */
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union hfsts6 {
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uint32_t raw;
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struct {
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uint32_t force_boot_guard_acm : 1;
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uint32_t cpu_debug_disable : 1;
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uint32_t bsp_init_disable : 1;
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uint32_t protect_bios_env : 1;
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uint32_t rsvd0 : 2;
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uint32_t error_enforce_policy : 2;
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uint32_t measured_boot : 1;
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uint32_t verified_boot : 1;
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uint32_t boot_guard_acmsvn : 4;
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uint32_t kmsvn : 4;
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uint32_t bpmsvn : 4;
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uint32_t key_manifest_id : 4;
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uint32_t boot_policy_status : 1;
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uint32_t error : 1;
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uint32_t boot_guard_disable : 1;
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uint32_t fpf_disable : 1;
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uint32_t fpf_soc_lock : 1;
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uint32_t txt_support : 1;
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} __packed fields;
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};
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static uint32_t me_read_config32(int offset)
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{
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return pci_read_config32(PCH_DEV_CSE, offset);
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}
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/*
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* From reading the documentation, this should work for both WHL and CML
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* platforms. Also, calling this function from dump_me_status() does not
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* work, as the ME does not respond and the command times out.
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*/
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static void print_me_version(void *unused)
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{
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struct mkhi_hdr {
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uint8_t group_id;
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uint8_t command :7;
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uint8_t is_resp :1;
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uint8_t rsvd;
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uint8_t result;
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} __packed;
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struct version {
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uint16_t minor;
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uint16_t major;
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uint16_t build;
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uint16_t hotfix;
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} __packed;
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struct fw_ver_resp {
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struct mkhi_hdr hdr;
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struct version code;
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struct version rec;
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struct version fitc;
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} __packed;
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union hfsts1 hfsts1;
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const struct mkhi_hdr fw_ver_msg = {
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.group_id = MKHI_GEN_GROUP_ID,
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.command = MKHI_GET_FW_VERSION,
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};
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struct fw_ver_resp resp;
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size_t resp_size = sizeof(resp);
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/* Ignore if UART debugging is disabled */
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if (!CONFIG(CONSOLE_SERIAL))
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return;
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hfsts1.raw = me_read_config32(PCI_ME_HFSTS1);
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/*
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* Prerequisites:
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* 1) HFSTS1 Current Working State is Normal
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* 2) HFSTS1 Current Operation Mode is Normal
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* 3) It's after DRAM INIT DONE message (taken care of by calling it
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* during ramstage
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*/
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if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) ||
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(hfsts1.fields.operation_mode != ME_OPMODE_NORMAL))
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goto fail;
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heci_reset();
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if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR,
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HECI_MKHI_ADDR))
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goto fail;
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if (!heci_receive(&resp, &resp_size))
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goto fail;
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if (resp.hdr.result)
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goto fail;
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printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major,
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resp.code.minor, resp.code.hotfix, resp.code.build);
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return;
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fail:
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printk(BIOS_DEBUG, "ME: Version: Unavailable\n");
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL);
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void dump_me_status(void)
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{
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union hfsts1 hfsts1;
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union hfsts2 hfsts2;
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union hfsts3 hfsts3;
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union hfsts4 hfsts4;
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union hfsts5 hfsts5;
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union hfsts6 hfsts6;
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hfsts1.raw = me_read_config32(PCI_ME_HFSTS1);
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hfsts2.raw = me_read_config32(PCI_ME_HFSTS2);
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hfsts3.raw = me_read_config32(PCI_ME_HFSTS3);
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hfsts4.raw = me_read_config32(PCI_ME_HFSTS4);
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hfsts5.raw = me_read_config32(PCI_ME_HFSTS5);
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hfsts6.raw = me_read_config32(PCI_ME_HFSTS6);
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printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n",
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hfsts1.raw);
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printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n",
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hfsts2.raw);
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printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n",
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hfsts3.raw);
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printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n",
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hfsts4.raw);
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printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n",
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hfsts5.raw);
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printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n",
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hfsts6.raw);
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printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n",
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hfsts1.fields.mfg_mode ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n",
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hfsts1.fields.fpt_bad ? "BAD" : "OK");
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printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n",
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hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n",
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hfsts1.fields.fw_init_complete ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n",
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hfsts1.fields.boot_options ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Update In Progress : %s\n",
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hfsts1.fields.fw_upd_in_progress ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n",
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hfsts1.fields.d0i3_support_valid ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n",
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hfsts2.fields.low_power_state ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n",
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hfsts2.fields.cpu_replaced ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n",
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hfsts2.fields.cpu_replaced_valid ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Current Working State : %u\n",
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hfsts1.fields.working_state);
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printk(BIOS_DEBUG, "ME: Current Operation State : %u\n",
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hfsts1.fields.operation_state);
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printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n",
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hfsts1.fields.operation_mode);
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printk(BIOS_DEBUG, "ME: Error Code : %u\n",
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hfsts1.fields.error_code);
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|
printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n",
|
||||||
|
hfsts6.fields.cpu_debug_disable ? "YES" : "NO");
|
||||||
|
printk(BIOS_DEBUG, "ME: TXT Support : %s\n",
|
||||||
|
hfsts6.fields.txt_support ? "YES" : "NO");
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue