mb/google/octopus: Create bobba variant
This creates a bobba variant for octopus. The devicetree overrides are copied from fleex, otherwise everything just defaults to baseboard settings. BUG=b:110781720 TEST=None Change-Id: Ic30c6b0d955ce26f4a9f40cd7fef1c429ab950fc Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -43,6 +43,7 @@ config VARIANT_DIR
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default "bip" if BOARD_GOOGLE_BIP
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default "phaser" if BOARD_GOOGLE_PHASER
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default "fleex" if BOARD_GOOGLE_FLEEX
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default "bobba" if BOARD_GOOGLE_BOBBA
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default "octopus" if BOARD_GOOGLE_OCTOPUS
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config DEVICETREE
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@ -59,6 +60,7 @@ config MAINBOARD_PART_NUMBER
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default "Bip" if BOARD_GOOGLE_BIP
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default "Phaser" if BOARD_GOOGLE_PHASER
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default "Fleex" if BOARD_GOOGLE_FLEEX
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default "Bobba" if BOARD_GOOGLE_BOBBA
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default "Octopus" if BOARD_GOOGLE_OCTOPUS
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config MAINBOARD_FAMILY
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@ -72,6 +74,7 @@ config GBB_HWID
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default "BIP TEST 5732" if BOARD_GOOGLE_BIP
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default "PHASER TEST 7167" if BOARD_GOOGLE_PHASER
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default "FLEEX TEST 7423" if BOARD_GOOGLE_FLEEX
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default "BOBBA TEST 4516" if BOARD_GOOGLE_BOBBA
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default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
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config MAX_CPUS
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@ -30,3 +30,10 @@ config BOARD_GOOGLE_FLEEX
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select BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS
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select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
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config BOARD_GOOGLE_BOBBA
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bool "-> Bobba"
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select BASEBOARD_OCTOPUS_LAPTOP
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select BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS
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select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <baseboard/gpio.h>
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#endif /* MAINBOARD_GPIO_H */
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@ -0,0 +1,48 @@
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chip soc/intel/apollolake
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device domain 0 on
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device pci 17.1 on
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chip drivers/i2c/da7219
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
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register "btn_cfg" = "50"
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register "mic_det_thr" = "500"
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register "jack_ins_deb" = "20"
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register "jack_det_rate" = ""32ms_64ms""
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register "jack_rem_deb" = "1"
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register "a_d_btn_thr" = "0xa"
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register "d_b_btn_thr" = "0x16"
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register "b_c_btn_thr" = "0x21"
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register "c_mic_btn_thr" = "0x3e"
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register "btn_avg" = "4"
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register "adc_1bit_rpt" = "1"
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register "micbias_lvl" = "2600"
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register "mic_amp_in_sel" = ""diff""
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device i2c 1a on end
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end
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end # - I2C 5
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device pci 17.2 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)"
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register "wake" = "GPE0_DW2_02"
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register "probed" = "1"
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device i2c 15 on end
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end
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end # - I2C 6
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device pci 17.3 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
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register "reset_delay_ms" = "20"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)"
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register "enable_delay_ms" = "1"
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register "has_power_resource" = "1"
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device i2c 10 on end
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end
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end # - I2C 7
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end
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end
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