mb/google/glados: clean up variant devicetrees
In preparation for conversion to overridetree format, clean up the variant devicetrees in order to minimize the differences across glados variants. This entails: - minor reformatting and reordering of devicetree entries - addition of setting default values on boards which skipped them - disabling unused I2C2 on boards which left it enabled - ensuring TCC offset set for all SKL-Y boards - setting VR mailbox command 1 for caroline - skipping init for UART2 on cave and glados - dropping unused PCIe RP5 for sentry Change-Id: I628b20a69fab187e67901c9eb98c0e2ddcb76b0d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier
parent
e4c784bd0d
commit
d957d12e6d
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@ -34,13 +34,23 @@ chip soc/intel/skylake
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register "dptf_enable" = "1"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "0"
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register "PttSwitch" = "0"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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@ -146,8 +156,6 @@ chip soc/intel/skylake
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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@ -163,6 +171,9 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# I2C4 is 1.8V
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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@ -61,8 +61,14 @@ chip soc/intel/skylake
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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# TCC offset
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register "tcc_offset" = "10"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Slew rate setting for improving audible noise
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register "AcousticNoiseMitigation" = "1"
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@ -137,7 +143,7 @@ chip soc/intel/skylake
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.voltage_limit = 1520,
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}"
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# Enable Root port 1.
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# Enable Root port 1
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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@ -160,7 +166,7 @@ chip soc/intel/skylake
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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@ -177,9 +183,15 @@ chip soc/intel/skylake
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# PL2 override 15W
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register "tdp_pl2_override" = "15"
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# Send an extra VR mailbox command for the supported MPS IMVP8 model
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register "SendVrMbxCmd" = "1"
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# TCC of 90C
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register "tcc_offset" = "10"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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@ -208,7 +220,7 @@ chip soc/intel/skylake
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device i2c 4a on end
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end
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end # I2C #1
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device pci 15.2 on end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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@ -167,7 +167,7 @@ chip soc/intel/skylake
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart0] = PchSerialIoPci,
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[PchSerialIoIndexUart1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart2] = PchSerialIoPci,
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# I2C4 is 1.8V
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@ -176,11 +176,12 @@ chip soc/intel/skylake
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# PL2 override 15W
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register "tdp_pl2_override" = "15"
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register "tcc_offset" = "10" # TCC of 90C
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# Send an extra VR mailbox command for the supported MPS IMVP8 model
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register "SendVrMbxCmd" = "1"
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# TCC of 90C
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register "tcc_offset" = "10"
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio_default" = "GPP_A7"
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@ -136,7 +136,7 @@ chip soc/intel/skylake
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.voltage_limit = 1520,
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}"
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# Enable Root port 1.
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# Enable Root port 1
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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@ -155,7 +155,6 @@ chip soc/intel/skylake
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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@ -172,17 +171,21 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# I2C4 is 1.8V
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
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# PL2 override 15W
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register "tdp_pl2_override" = "15"
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register "tcc_offset" = "10" # TCC of 90C
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# Send an extra VR mailbox command for the supported MPS IMVP8 model
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register "SendVrMbxCmd" = "1"
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# TCC of 90C
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register "tcc_offset" = "10"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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@ -136,7 +136,7 @@ chip soc/intel/skylake
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.voltage_limit = 1520,
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}"
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# Enable Root port 1.
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# Enable Root port 1
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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@ -155,8 +155,6 @@ chip soc/intel/skylake
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 1
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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@ -169,15 +167,21 @@ chip soc/intel/skylake
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart0] = PchSerialIoPci,
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[PchSerialIoIndexUart1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart2] = PchSerialIoPci,
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# I2C4 is 1.8V
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
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# PL2 override 15W
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register "tdp_pl2_override" = "15"
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# Send an extra VR mailbox command for the supported MPS IMVP8 model
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register "SendVrMbxCmd" = "1"
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# TCC of 90C
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register "tcc_offset" = "10"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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@ -9,6 +9,8 @@ chip soc/intel/skylake
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register "gpu_pch_backlight_pwm_hz" = "1000"
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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@ -32,13 +34,23 @@ chip soc/intel/skylake
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register "dptf_enable" = "1"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "0"
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register "PttSwitch" = "0"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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@ -124,7 +136,7 @@ chip soc/intel/skylake
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.voltage_limit = 1520,
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}"
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# Enable Root port 1.
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# Enable Root port 1
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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@ -143,8 +155,6 @@ chip soc/intel/skylake
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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@ -160,6 +170,9 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# I2C4 is 1.8V
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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@ -34,13 +34,23 @@ chip soc/intel/skylake
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register "dptf_enable" = "1"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "2"
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register "PttSwitch" = "0"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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@ -126,14 +136,18 @@ chip soc/intel/skylake
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.voltage_limit = 1520,
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}"
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# Enable Root port 1 and 5.
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# Enable Root port 1
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[4]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
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# RP 1 uses SRCCLKREQ1#
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register "PcieRpClkReqNumber[0]" = "1"
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# Enable Root port 5
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register "PcieRpEnable[4]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[4]" = "1"
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# RP 5 uses SRCCLKREQ2#
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register "PcieRpClkReqNumber[4]" = "2"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
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@ -148,9 +162,6 @@ chip soc/intel/skylake
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
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register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # I2C0 is 3.3V
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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@ -166,6 +177,12 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# I2C0 is 3.3V
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register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
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# I2C4 is 1.8V
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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@ -263,7 +280,7 @@ chip soc/intel/skylake
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on end # PCI Express Port 5
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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