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siemens/mc_apl1: Add legacy IRQ routing for PCI devices 

On this mainboard there are PCI devices, which are connected to the PCIe
root port via a PCIe-2-PCI bridge. One of the devices only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 4 (Device 14.0).

The following routing is required:
INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#->PIRQA#

Change-Id: I5464c9a2669773bc1e6cd4b4d29d1be838dbfa27
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2017-10-23 16:10:04 +02:00 committed by Werner Zeh
parent d0e51330ed
commit d958300590
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/siemens/mc_apl1/mainboard.c
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@ -21,7 +21,9 @@
#include <hwilib.h> #include <hwilib.h>
#include <i210.h> #include <i210.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <string.h> #include <string.h>
#include <bootstate.h> #include <bootstate.h>
#include <timer.h> #include <timer.h>
@ -142,6 +144,12 @@ static void mainboard_final(void *chip_info)
cmd |= PCI_COMMAND_MASTER; cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd); pci_write_config16(dev, PCI_COMMAND, cmd);
} }
/*
* PIR6 register mapping for PCIe root ports
* INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
*/
pcr_write16(PID_ITSS, 0x314c, 0x0321);
} }
static void wait_for_legacy_dev(void *unused) static void wait_for_legacy_dev(void *unused)