mb/google/rex: Create ovis variant
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jakub Czapiga
Felix Held
parent
50c201a102
commit
d95d2645f4
15 changed files with 349 additions and 1 deletions
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@ -43,11 +43,24 @@ config BOARD_GOOGLE_BASEBOARD_REX
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select SYSTEM_TYPE_LAPTOP
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select TPM_GOOGLE_TI50
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config BOARD_GOOGLE_BASEBOARD_OVIS
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def_bool n
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select BOARD_GOOGLE_REX_COMMON
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select DRIVERS_INTEL_PMC
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select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
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select HAVE_SLP_S0_GATE
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select MAINBOARD_HAS_CHROMEOS
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select MEMORY_SOLDERDOWN
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select SOC_INTEL_METEORLAKE
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select TPM_GOOGLE_TI50
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if BOARD_GOOGLE_REX_COMMON
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config BASEBOARD_DIR
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string
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default "rex" if BOARD_GOOGLE_BASEBOARD_REX
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default "ovis" if BOARD_GOOGLE_BASEBOARD_OVIS
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config CHROMEOS
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select EC_GOOGLE_CHROMEEC_SWITCHES
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@ -79,17 +92,20 @@ config MAINBOARD_DIR
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config MAINBOARD_FAMILY
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string
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default "Google_Rex" if BOARD_GOOGLE_BASEBOARD_REX
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default "Google_Ovis" if BOARD_GOOGLE_BASEBOARD_OVIS
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config MAINBOARD_PART_NUMBER
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default "Rex" if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_REX_EC_ISH
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default "Screebo" if BOARD_GOOGLE_SCREEBO
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default "Karis" if BOARD_GOOGLE_KARIS
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default "Ovis" if BOARD_GOOGLE_OVIS
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config VARIANT_DIR
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string
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default "rex0" if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_REX_EC_ISH
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default "screebo" if BOARD_GOOGLE_SCREEBO
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default "karis" if BOARD_GOOGLE_KARIS
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default "ovis" if BOARD_GOOGLE_OVIS
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config DIMM_SPD_SIZE
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default 512
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@ -112,7 +128,7 @@ config OVERRIDE_DEVICETREE
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x4 if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_SCREEBO || BOARD_GOOGLE_REX_EC_ISH
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default 0x4 if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_SCREEBO || BOARD_GOOGLE_REX_EC_ISH || BOARD_GOOGLE_OVIS
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config DRIVER_TPM_I2C_ADDR
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hex
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@ -28,3 +28,7 @@ config BOARD_GOOGLE_REX_EC_ISH
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_SOUNDWIRE_CS42L42
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select DRIVERS_SOUNDWIRE_MAX98363
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config BOARD_GOOGLE_OVIS
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bool "-> Ovis"
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select BOARD_GOOGLE_BASEBOARD_OVIS
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@ -0,0 +1 @@
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romstage-y += memory.c
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@ -0,0 +1,69 @@
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chip soc/intel/meteorlake
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# GPE configuration
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_E"
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register "pmc_gpe0_dw2" = "GPP_F"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1
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register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4
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register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
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register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8
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register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9
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register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0
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register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1
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register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0
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register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1
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register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
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register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
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# S0ix enable
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register "s0ix_enable" = "1"
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# DPTF enable
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register "dptf_enable" = "1"
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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# Set on-board graphics as primary display
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register "skip_ext_gfx_scan" = "1"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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register "pch_hda_dsp_enable" = "1"
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register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
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register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
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register "pch_hda_idisp_codec_enable" = "1"
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device domain 0 on
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device ref igpu on end
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device ref dtt on end
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device ref xhci on end
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device ref shared_sram on end
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device ref heci1 on end
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device ref uart0 on end
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device ref soc_espi on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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end
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end
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@ -0,0 +1,64 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __BASEBOARD_EC_H__
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#define __BASEBOARD_EC_H__
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <baseboard/gpio.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
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#define MAINBOARD_EC_SMI_EVENTS \
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(EC_HOST_EVENT_NONE)
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/* EC can wake from S5 with power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/*
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* EC can wake from S3/S0ix with:
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* 1. AC Connect/Disconnect
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* 2. Power button
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* 3. Key press
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* 4. Mode change
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*/
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#define MAINBOARD_EC_S3_WAKE_EVENTS \
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(MAINBOARD_EC_S5_WAKE_EVENTS |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
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(MAINBOARD_EC_S3_WAKE_EVENTS |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable EC backed ALS device in ACPI */
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#define EC_ENABLE_ALS_DEVICE
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/* Enable MKBP for buttons and switches */
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#define EC_ENABLE_MKBP_DEVICE
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
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#endif /* __BASEBOARD_EC_H__ */
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@ -0,0 +1,26 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* WP signal to PCH */
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#define GPIO_PCH_WP GPP_H10
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/* GPIO IRQ for tight timestamps / wake support */
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#define EC_SYNC_IRQ GPP_A17_IRQ
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/* eSPI virtual wire reporting */
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#define EC_SCI_GPI GPE0_ESPI
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/* Used to gate SoC's SLP_S0# signal */
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#define GPIO_SLP_S0_GATE GPP_H14
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/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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/* Memory configuration board straps */
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#define GPIO_MEM_CONFIG_0 GPP_E11
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#define GPIO_MEM_CONFIG_1 GPP_E02
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#define GPIO_MEM_CONFIG_2 GPP_E01
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#define GPIO_MEM_CONFIG_3 GPP_E12
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#define GPIO_MEM_CH_SEL GPP_E13
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#endif /* __BASEBOARD_GPIO_H__ */
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96
src/mainboard/google/rex/variants/baseboard/ovis/memory.c
Normal file
96
src/mainboard/google/rex/variants/baseboard/ovis/memory.c
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@ -0,0 +1,96 @@
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/* SPDX-License-Identifier: GPL-3.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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static const struct mb_cfg baseboard_memcfg = {
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.type = MEM_TYPE_LP5X,
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.rcomp = {
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/* Baseboard uses only 100ohm Rcomp resistors */
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.resistor = 100,
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},
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/* DQ byte map */
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.lpx_dq_map = {
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.ddr0 = {
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.dq0 = { 7, 1, 2, 0, 3, 6, 5, 4 },
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.dq1 = { 13, 12, 14, 15, 8, 9, 10, 11 },
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},
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.ddr1 = {
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.dq0 = { 10, 9, 11, 8, 15, 13, 14, 12 },
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.dq1 = { 6, 0, 7, 4, 3, 1, 2, 5 },
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},
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.ddr2 = {
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.dq0 = { 11, 10, 8, 9, 12, 15, 14, 13 },
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.dq1 = { 7, 0, 6, 5, 3, 2, 1, 4 },
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},
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.ddr3 = {
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.dq0 = { 13, 10, 8, 9, 14, 11, 15, 12 },
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.dq1 = { 1, 6, 4, 7, 0, 5, 2, 3 },
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},
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.ddr4 = {
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.dq0 = { 10, 11, 9, 12, 13, 14, 15, 8 },
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.dq1 = { 6, 7, 4, 5, 1, 0, 3, 2 },
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},
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.ddr5 = {
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.dq0 = { 0, 5, 3, 6, 1, 4, 2, 7 },
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.dq1 = { 8, 11, 10, 9, 15, 14, 13, 12 },
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},
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.ddr6 = {
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.dq0 = { 1, 3, 0, 2, 6, 5, 7, 4 },
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.dq1 = { 13, 15, 14, 12, 11, 10, 8, 9 },
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},
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.ddr7 = {
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.dq0 = { 10, 9, 11, 8, 12, 15, 14, 13 },
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.dq1 = { 6, 4, 7, 5, 2, 1, 0, 3 },
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},
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},
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/* DQS CPU<>DRAM map */
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.lpx_dqs_map = {
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.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
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.ddr2 = { .dqs0 = 1, .dqs1 = 0 },
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.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
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.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
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.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr7 = { .dqs0 = 1, .dqs1 = 0 },
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},
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.lp5x_config = {
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.ccc_config = 0x66,
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},
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.ect = 1, /* Early Command Training */
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};
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const struct mb_cfg *__weak variant_memory_params(void)
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{
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return &baseboard_memcfg;
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}
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int __weak variant_memory_sku(void)
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{
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gpio_t spd_gpios[] = {
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GPIO_MEM_CONFIG_0,
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GPIO_MEM_CONFIG_1,
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GPIO_MEM_CONFIG_2,
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GPIO_MEM_CONFIG_3,
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};
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return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
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}
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bool __weak variant_is_half_populated(void)
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{
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return gpio_get(GPIO_MEM_CH_SEL);
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}
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void __weak variant_get_spd_info(struct mem_spd *spd_info)
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{
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spd_info->topo = MEM_TOPO_MEMORY_DOWN;
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spd_info->cbfs_index = variant_memory_sku();
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}
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3
src/mainboard/google/rex/variants/ovis/Makefile.inc
Normal file
3
src/mainboard/google/rex/variants/ovis/Makefile.inc
Normal file
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@ -0,0 +1,3 @@
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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30
src/mainboard/google/rex/variants/ovis/gpio.c
Normal file
30
src/mainboard/google/rex/variants/ovis/gpio.c
Normal file
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <types.h>
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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const struct pad_config *variant_gpio_table(size_t *num)
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{
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*num = 0;
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return NULL;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = 0;
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return NULL;
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}
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static const struct cros_gpio cros_gpios[] = {
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};
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DECLARE_CROS_GPIOS(cros_gpios);
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = 0;
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return NULL;
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}
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/ec.h>
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#endif /* MAINBOARD_GPIO_H */
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __MAINBOARD_GPIO_H__
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#define __MAINBOARD_GPIO_H__
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#include <baseboard/gpio.h>
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#endif /* __MAINBOARD_GPIO_H__ */
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
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SPD_SOURCES = placeholder
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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DRAM Part Name ID to assign
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@ -0,0 +1,11 @@
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# This is a CSV file containing a list of memory parts used by this variant.
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# One part per line with an optional fixed ID in column 2.
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||||
# Only include a fixed ID if it is required for legacy reasons!
|
||||
# Generated IDs are dependent on the order of parts in this file,
|
||||
# so new parts must always be added at the end of the file!
|
||||
#
|
||||
# Generate an updated Makefile.inc and dram_id.generated.txt by running the
|
||||
# part_id_gen tool from util/spd_tools.
|
||||
# See util/spd_tools/README.md for more details and instructions.
|
||||
|
||||
# Part Name
|
||||
4
src/mainboard/google/rex/variants/ovis/overridetree.cb
Normal file
4
src/mainboard/google/rex/variants/ovis/overridetree.cb
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
chip soc/intel/meteorlake
|
||||
device domain 0 on
|
||||
end
|
||||
end
|
||||
Loading…
Reference in a new issue