lp4x: Add new memory parts and generate SPDs

This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL:
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E

BUG=b:159195585,b:152936481,b:156435028
TEST=build.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt

@@ -11,3 +11,5 @@ K4U6E3S4AA-MGCR,spd-1.hex
 MT53E512M32D2NP-046 WT:E,spd-1.hex
 H9HCNNNCPMMLXR-NEE,spd-3.hex
 K4UBE3D4AA-MGCR,spd-3.hex
+MT53E512M64D4NW-046 WT:E,spd-1.hex
+MT53E1G64D8NW-046 WT:E,spd-3.hex

util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt

@@ -157,6 +157,30 @@
                 "ranksPerChannel": 2,
                 "speedMbps": 4267
             }
+        },
+        {
+            "name": "MT53E512M64D4NW-046 WT:E",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        },
+        {
+            "name": "MT53E1G64D8NW-046 WT:E",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 4,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 4267
+            }
         }
     ]
 }