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glados: Clean up devicetree.cb 

Clean up the PCI device list comments to be consistent between
the skylake mainboards.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I0080ab21db006365f34995db06480dae68ac547d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d
Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297338
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11561
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2015-09-03 16:04:09 -07:00 committed by Patrick Georgi
parent e031ec3ca3
commit d96f830786
1 changed files with 73 additions and 67 deletions
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140
src/mainboard/google/glados/devicetree.cb
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@ -5,6 +5,63 @@ chip soc/intel/skylake
register "deep_s5_enable" = "1" register "deep_s5_enable" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "IshEnable" = "0"
register "PttSwitch" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
register "PortUsb20Enable[0]" = "1" # Type-C Port 1
register "PortUsb20Enable[1]" = "1" # Type-C Port 2
register "PortUsb20Enable[2]" = "1" # Bluetooth
register "PortUsb20Enable[4]" = "1" # Type-A Port 1
register "PortUsb20Enable[6]" = "1" # Camera
register "PortUsb20Enable[8]" = "1" # Type-A Port 2
register "PortUsb30Enable[0]" = "1" # Type-C Port 1
register "PortUsb30Enable[1]" = "1" # Type-C Port 2
register "PortUsb30Enable[2]" = "1" # Type-A Port 1
register "PortUsb30Enable[3]" = "1" # Type-A Port 2
# Must leave UART0 enabled or SD/eMMC will not work as PCI # Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \ register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
@ -20,80 +77,28 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoPci, \ [PchSerialIoIndexUart2] = PchSerialIoPci, \
}" }"
register "PortUsb20Enable[0]" = "1" # Type-C Port 1
register "PortUsb20Enable[1]" = "1" # Type-C Port 2
register "PortUsb20Enable[2]" = "1" # Bluetooth
register "PortUsb20Enable[4]" = "1" # Type-A Port 1
register "PortUsb20Enable[6]" = "1" # Camera
register "PortUsb20Enable[8]" = "1" # Type-A Port 2
register "PortUsb30Enable[0]" = "1" # Type-C Port 1
register "PortUsb30Enable[1]" = "1" # Type-C Port 2
register "PortUsb30Enable[2]" = "1" # Type-A Port 1
register "PortUsb30Enable[3]" = "1" # Type-A Port 2
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ProbelessTrace" = "0"
register "EnableTraceHub" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "IshEnable" = "0"
register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# Embedded Controller host command window
register "gen1_dec" = "0x00fc0801"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device
device pci 14.0 on end # USB 3.0 xHCI Controller device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB Device Controller (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem device pci 14.2 on end # Thermal Subsystem
device pci 15.0 on end # I2C Controller #0 device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C Controller #1 device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C Controller #2 device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C Controller #3 device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Intel MEI #3 device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on end # SATA Controller device pci 17.0 off end # SATA
device pci 19.0 on end # UART Controller #2 device pci 19.0 on end # UART #2
device pci 19.1 off end # I2C Controller #5 device pci 19.1 off end # I2C #5
device pci 19.2 on end # I2C Controller #4 device pci 19.2 on end # I2C #4
device pci 1c.0 on end # PCI Express Port 1 device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2 device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3 device pci 1c.2 off end # PCI Express Port 3
@ -111,6 +116,7 @@ chip soc/intel/skylake
device pci 1e.2 off end # GSPI #0 device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1 device pci 1e.3 off end # GSPI #1
device pci 1e.4 on end # eMMC device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard device pci 1e.6 on end # SDCard
device pci 1f.0 on device pci 1f.0 on
chip drivers/pc80/tpm chip drivers/pc80/tpm
@ -121,9 +127,9 @@ chip soc/intel/skylake
end end
end # LPC Interface end # LPC Interface
device pci 1f.2 on end # Power Management Controller device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel High Definition Audio device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus Controller device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE Controller device pci 1f.6 off end # GbE
end end
end end