glados: Clean up devicetree.cb
Clean up the PCI device list comments to be consistent between the skylake mainboards. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0080ab21db006365f34995db06480dae68ac547d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297338 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11561 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
e031ec3ca3
commit
d96f830786
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@ -5,6 +5,63 @@ chip soc/intel/skylake
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register "deep_s5_enable" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_C"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command range is in 0x800-0x8ff
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register "gen1_dec" = "0x00fc0801"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "2"
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register "IshEnable" = "0"
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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# Enable Root port 1 and 5.
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[4]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
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register "PcieRpClkReqNumber[0]" = "1"
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register "PcieRpClkReqNumber[4]" = "2"
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register "PortUsb20Enable[0]" = "1" # Type-C Port 1
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register "PortUsb20Enable[1]" = "1" # Type-C Port 2
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register "PortUsb20Enable[2]" = "1" # Bluetooth
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register "PortUsb20Enable[4]" = "1" # Type-A Port 1
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register "PortUsb20Enable[6]" = "1" # Camera
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register "PortUsb20Enable[8]" = "1" # Type-A Port 2
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register "PortUsb30Enable[0]" = "1" # Type-C Port 1
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register "PortUsb30Enable[1]" = "1" # Type-C Port 2
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register "PortUsb30Enable[2]" = "1" # Type-A Port 1
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register "PortUsb30Enable[3]" = "1" # Type-A Port 2
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{ \
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[PchSerialIoIndexI2C0] = PchSerialIoPci, \
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@ -20,80 +77,28 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoPci, \
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}"
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register "PortUsb20Enable[0]" = "1" # Type-C Port 1
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register "PortUsb20Enable[1]" = "1" # Type-C Port 2
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register "PortUsb20Enable[2]" = "1" # Bluetooth
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register "PortUsb20Enable[4]" = "1" # Type-A Port 1
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register "PortUsb20Enable[6]" = "1" # Camera
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register "PortUsb20Enable[8]" = "1" # Type-A Port 2
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register "PortUsb30Enable[0]" = "1" # Type-C Port 1
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register "PortUsb30Enable[1]" = "1" # Type-C Port 2
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register "PortUsb30Enable[2]" = "1" # Type-A Port 1
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register "PortUsb30Enable[3]" = "1" # Type-A Port 2
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# Enable Root port 1 and 5.
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[4]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
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register "PcieRpClkReqNumber[0]" = "1"
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register "PcieRpClkReqNumber[4]" = "2"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "1"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "ProbelessTrace" = "0"
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register "EnableTraceHub" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "IshEnable" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "PttSwitch" = "0"
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register "SkipExtGfxScan" = "1"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_C"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# Embedded Controller host command window
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register "gen1_dec" = "0x00fc0801"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB 3.0 xHCI Controller
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device pci 14.1 off end # USB Device Controller (OTG)
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on end # I2C Controller #0
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device pci 15.1 on end # I2C Controller #1
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device pci 15.2 off end # I2C Controller #2
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device pci 15.3 off end # I2C Controller #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Intel MEI #3
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device pci 17.0 on end # SATA Controller
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device pci 19.0 on end # UART Controller #2
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device pci 19.1 off end # I2C Controller #5
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device pci 19.2 on end # I2C Controller #4
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 off end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # I2C #4
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device pci 1c.0 on end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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@ -111,6 +116,7 @@ chip soc/intel/skylake
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1e.4 on end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 on end # SDCard
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device pci 1f.0 on
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chip drivers/pc80/tpm
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@ -121,9 +127,9 @@ chip soc/intel/skylake
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end
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end # LPC Interface
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel High Definition Audio
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device pci 1f.4 on end # SMBus Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE Controller
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device pci 1f.6 off end # GbE
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end
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end
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