From d97d860f232571aca755aca88ffa72d2f3fb87c8 Mon Sep 17 00:00:00 2001 From: Rex Chou Date: Thu, 20 Jul 2023 14:00:24 +0800 Subject: [PATCH] mb/google/nissa/var/craaskov: Configure GPIOs according to schematics Configure GPIOs based on schematics and confirm with EE. BUG=b:290248526 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb Signed-off-by: Rex Chou Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636 Tested-by: build bot (Jenkins) Reviewed-by: Derek Huang Reviewed-by: Eric Lai Reviewed-by: Ian Feng Reviewed-by: Sumeet R Pawnikar --- .../brya/variants/craaskov/Makefile.inc | 4 + .../google/brya/variants/craaskov/gpio.c | 78 +++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 src/mainboard/google/brya/variants/craaskov/Makefile.inc create mode 100644 src/mainboard/google/brya/variants/craaskov/gpio.c diff --git a/src/mainboard/google/brya/variants/craaskov/Makefile.inc b/src/mainboard/google/brya/variants/craaskov/Makefile.inc new file mode 100644 index 0000000000..760ef23ebd --- /dev/null +++ b/src/mainboard/google/brya/variants/craaskov/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/craaskov/gpio.c b/src/mainboard/google/brya/variants/craaskov/gpio.c new file mode 100644 index 0000000000..f3ed2c56d4 --- /dev/null +++ b/src/mainboard/google/brya/variants/craaskov/gpio.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A21 : GPP_A21 ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A21 : GPP_A22 ==> NC */ + PAD_NC(GPP_A22, NONE), + /* B5 : I2C2_SDA ==> TOF_I2C_DAT */ + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF1, LOCK_CONFIG), + /* B6 : I2C2_SCL ==> TOF_I2C_CLK */ + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF1, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F13 : SOC_PEN_DETECT_R_ODL ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F15 : SOC_PEN_DETECT_ODL ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* H8 : CNV_MFUART2_RXD ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : CNV_MFUART2_TXD ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H19 : SRCCLKREQ4# ==> TOF_INT# */ + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, EDGE_BOTH), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* R6 : DMIC_CLK_A_1A ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : DMIC_DATA_1A ==> NC */ + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +}