soc/intel/jasperlake: Fix PMC_GPE_DW mapping

PMC_GPE_DW mapping was not configured correctly and hence
coreboot skipped programming Tier 1 GPIOs resulting in failure of
S3 wake from Trackpad.

TEST=System should wake from S3 via trackpad

Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>

src/soc/intel/jasperlake/gpio.c

@@ -182,14 +182,15 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 	static const struct pmc_to_gpio_route routes[] = {
 		{ PMC_GPP_A, GPP_A },
 		{ PMC_GPP_B, GPP_B },
+		{ PMC_GPP_G, GPP_G },
+		{ PMC_GPP_C, GPP_C },
 		{ PMC_GPP_R, GPP_R },
 		{ PMC_GPP_D, GPP_D },
 		{ PMC_GPP_S, GPP_S },
 		{ PMC_GPP_H, GPP_H },
+		{ PMC_GPP_F, GPP_F },
 		{ PMC_GPD,   GPP_GPD },
-		{ PMC_GPP_C, GPP_C },
+		{ PMC_GPP_E, GPP_E }
-		{ PMC_GPP_E, GPP_E },
-		{ PMC_GPP_F, GPP_F }
 	};
 
 	*num = ARRAY_SIZE(routes);

src/soc/intel/jasperlake/include/soc/pmc.h

@@ -102,16 +102,17 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
-#define  PMC_GPP_A			0x0
+#define  PMC_GPP_G			0x0
 #define  PMC_GPP_B			0x1
-#define  PMC_GPP_F			0x2
+#define  PMC_GPP_A			0x2
-#define  PMC_GPD			0x3
+#define  PMC_GPP_R			0x3
-#define  PMC_GPP_R			0x4
+#define  PMC_GPP_S			0x4
-#define  PMC_GPP_S			0x6
+#define  PMC_GPD			0x5
+#define  PMC_GPP_H			0x6
 #define  PMC_GPP_D			0x7
-#define  PMC_GPP_C			0x8
+#define  PMC_GPP_F			0x8
-#define  PMC_GPP_H			0xA
+#define  PMC_GPP_C			0xA
-#define  PMC_GPP_E			0xF
+#define  PMC_GPP_E			0xB
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)