From d981c49038024cc9679114b92cadec51308b9ba8 Mon Sep 17 00:00:00 2001 From: Matt Papageorge Date: Wed, 19 May 2021 10:04:27 -0500 Subject: [PATCH] mb/google/mancomb: Enable some PCIe power saving features Enable ASPM, Common Clock and Clock Power Managment. Accomplish this by adding the options in the platform Kconfig as well as dxio descriptors. BUG=b:187743927 TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci Change-Id: I9d6e606763798afc6b797d7d24ee7cae09f9e33f Signed-off-by: Matt Papageorge Reviewed-on: https://review.coreboot.org/c/coreboot/+/54681 Reviewed-by: Raul Rangel Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/mancomb/Kconfig | 3 +++ src/mainboard/google/mancomb/port_descriptors.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index 3d798efe4c..de17454ee9 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -28,6 +28,9 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK select PSP_DISABLE_POSTCODES select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_USE_ESPI diff --git a/src/mainboard/google/mancomb/port_descriptors.c b/src/mainboard/google/mancomb/port_descriptors.c index b992906c9b..30996e951e 100644 --- a/src/mainboard/google/mancomb/port_descriptors.c +++ b/src/mainboard/google/mancomb/port_descriptors.c @@ -12,6 +12,7 @@ static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = { .end_logical_lane = 0, .device_number = 2, .function_number = 1, + .link_aspm = ASPM_L1, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, .gpio_group_id = GPIO_29, @@ -24,6 +25,7 @@ static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = { .end_logical_lane = 1, .device_number = 2, .function_number = 2, + .link_aspm = ASPM_L1, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, .gpio_group_id = GPIO_70, @@ -36,6 +38,7 @@ static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = { .end_logical_lane = 2, .device_number = 2, .function_number = 3, + .link_aspm = ASPM_L1, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, .gpio_group_id = GPIO_18, @@ -48,6 +51,7 @@ static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = { .end_logical_lane = 7, .device_number = 2, .function_number = 4, + .link_aspm = ASPM_L1, .turn_off_unused_lanes = true, .clk_req = CLK_REQ3, .gpio_group_id = GPIO_40,