nb/intel/haswell: Confine `pei_data` uses to raminit.c
Reorganize romstage.c to resemble sandybridge, and move everything that needs `pei_data` into raminit.c function `perform_raminit`. Barring USB settings, coreboot code no longer depends on pei_data.h definitions. It still depends on MRC, though. For now. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I433f88db5fe7a7533ab6837015647ec31fb45e88 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51449 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Patrick Georgi
parent
8d529421d3
commit
d99b693c96
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@ -9,13 +9,18 @@
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#include <ip_checksum.h>
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#include <memory_info.h>
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#include <mrc_cache.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/dram/ddr3.h>
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#include <northbridge/intel/haswell/chip.h>
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#include <smbios.h>
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#include <spd.h>
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#include <security/vboot/vboot_common.h>
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#include <commonlib/region.h>
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#include <southbridge/intel/lynxpoint/me.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <timestamp.h>
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#include <types.h>
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#include "raminit.h"
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@ -24,7 +29,7 @@
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#define MRC_CACHE_VERSION 1
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void save_mrc_data(struct pei_data *pei_data)
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static void save_mrc_data(struct pei_data *pei_data)
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{
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/* Save the MRC S3 restore data to cbmem */
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output,
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@ -105,7 +110,7 @@ static void report_memory_config(void)
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*
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* @param pei_data: configuration data for UEFI PEI reference code
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*/
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void sdram_initialize(struct pei_data *pei_data)
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static void sdram_initialize(struct pei_data *pei_data)
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{
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int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1)));
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@ -206,7 +211,7 @@ static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a)
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return (ddrsz / 2) * nb_slots_per_channel(capid0_a);
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}
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void setup_sdram_meminfo(struct pei_data *pei_data)
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static void setup_sdram_meminfo(struct pei_data *pei_data)
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{
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struct memory_info *mem_info;
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struct dimm_info *dimm;
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@ -261,3 +266,116 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
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mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
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mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a);
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}
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/* Copy SPD data for on-board memory */
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static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
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{
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if (!CONFIG(HAVE_SPD_IN_CBFS))
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return;
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printk(BIOS_DEBUG, "SPD index %d\n", spdi->spd_index);
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size_t spd_file_len;
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uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
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if (!spd_file)
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die("SPD data not found.");
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if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
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printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
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spdi->spd_index = 0;
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}
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if (spd_file_len < SPD_LEN)
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die("Missing SPD data.");
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/* MRC only uses index 0, but coreboot uses the other indices */
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memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
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for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
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if (spdi->addresses[i] == SPD_MEMORY_DOWN)
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memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
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}
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}
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/*
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* 0 = leave channel enabled
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* 1 = disable dimm 0 on channel
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* 2 = disable dimm 1 on channel
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* 3 = disable dimm 0+1 on channel
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*/
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static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
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{
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return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
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}
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void perform_raminit(const int s3resume)
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{
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const struct device *gbe = pcidev_on_root(0x19, 0);
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const struct northbridge_intel_haswell_config *cfg = config_of_soc();
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struct pei_data pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.hpet_address = CONFIG_HPET_ADDRESS,
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.rcba = CONFIG_FIXED_RCBA_MMIO_BASE,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.temp_mmio_base = 0xfed08000,
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.system_type = get_pch_platform_type(),
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.ec_present = cfg->ec_present,
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.gbe_enable = gbe && gbe->enabled,
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.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
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.dq_pins_interleaved = cfg->dq_pins_interleaved,
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.max_ddr3_freq = 1600,
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.usb_xhci_on_resume = cfg->usb_xhci_on_resume,
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};
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memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports));
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memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports));
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/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
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pei_data.boot_mode = s3resume ? 2 : 0;
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/* Obtain the SPD addresses from mainboard code */
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struct spd_info spdi = {0};
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mb_get_spd_map(&spdi);
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for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++)
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pei_data.spd_addresses[i] = spdi.addresses[i];
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/* Calculate unimplemented DIMM slots for each channel */
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pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
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pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
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timestamp_add_now(TS_BEFORE_INITRAM);
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copy_spd(&pei_data, &spdi);
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sdram_initialize(&pei_data);
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timestamp_add_now(TS_AFTER_INITRAM);
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post_code(0x3b);
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intel_early_me_status();
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int cbmem_was_initted = !cbmem_recovery(s3resume);
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if (s3resume && !cbmem_was_initted) {
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/* Failed S3 resume, reset to come up cleanly */
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printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
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system_reset();
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}
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/* Save data returned from MRC on non-S3 resumes. */
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if (!s3resume)
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save_mrc_data(&pei_data);
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setup_sdram_meminfo(&pei_data);
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}
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@ -20,10 +20,6 @@ extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS];
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/* Mainboard callback to fill in the SPD addresses in MRC format */
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void mb_get_spd_map(struct spd_info *spdi);
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void sdram_initialize(struct pei_data *pei_data);
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void setup_sdram_meminfo(struct pei_data *pei_data);
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/* save_mrc_data() must be called after cbmem has been initialized. */
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void save_mrc_data(struct pei_data *pei_data);
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void perform_raminit(const int s3resume);
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#endif /* RAMINIT_H */
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@ -1,153 +1,51 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/romstage.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <cf9_reset.h>
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#include <device/device.h>
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#include <device/mmio.h>
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#include <elog.h>
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#include <timestamp.h>
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#include <cpu/x86/lapic.h>
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#include <cbmem.h>
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#include <commonlib/helpers.h>
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#include <romstage_handoff.h>
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#include <security/intel/txt/txt.h>
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#include <security/intel/txt/txt_register.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/chip.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <southbridge/intel/lynxpoint/me.h>
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#include <string.h>
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#include <types.h>
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/* Copy SPD data for on-board memory */
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static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
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{
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if (!CONFIG(HAVE_SPD_IN_CBFS))
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return;
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printk(BIOS_DEBUG, "SPD index %d\n", spdi->spd_index);
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size_t spd_file_len;
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uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
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if (!spd_file)
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die("SPD data not found.");
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if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
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printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
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spdi->spd_index = 0;
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}
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if (spd_file_len < SPD_LEN)
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die("Missing SPD data.");
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/* MRC only uses index 0, but coreboot uses the other indices */
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memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
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for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
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if (spdi->addresses[i] == SPD_MEMORY_DOWN)
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memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
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}
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}
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void __weak mb_late_romstage_setup(void)
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{
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}
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/*
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* 0 = leave channel enabled
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* 1 = disable dimm 0 on channel
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* 2 = disable dimm 1 on channel
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* 3 = disable dimm 0+1 on channel
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*/
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static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
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{
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return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
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}
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/* The romstage entry point for this platform is not mainboard-specific, hence the name */
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void mainboard_romstage_entry(void)
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{
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const struct device *gbe = pcidev_on_root(0x19, 0);
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const struct northbridge_intel_haswell_config *cfg = config_of_soc();
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struct pei_data pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.hpet_address = CONFIG_HPET_ADDRESS,
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.rcba = CONFIG_FIXED_RCBA_MMIO_BASE,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.temp_mmio_base = 0xfed08000,
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.system_type = get_pch_platform_type(),
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.ec_present = cfg->ec_present,
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.gbe_enable = gbe && gbe->enabled,
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.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
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.dq_pins_interleaved = cfg->dq_pins_interleaved,
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.max_ddr3_freq = 1600,
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.usb_xhci_on_resume = cfg->usb_xhci_on_resume,
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};
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memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports));
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memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports));
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enable_lapic();
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early_pch_init();
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const int s3resume = southbridge_detect_s3_resume();
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elog_boot_notify(s3resume);
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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*/
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haswell_early_initialization();
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printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
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const int s3resume = southbridge_detect_s3_resume();
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elog_boot_notify(s3resume);
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/* Prepare USB controller early in S3 resume */
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if (s3resume)
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enable_usb_bar();
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post_code(0x3a);
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/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
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pei_data.boot_mode = s3resume ? 2 : 0;
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/* Obtain the SPD addresses from mainboard code */
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struct spd_info spdi = {0};
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mb_get_spd_map(&spdi);
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for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++)
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pei_data.spd_addresses[i] = spdi.addresses[i];
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/* Calculate unimplemented DIMM slots for each channel */
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pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
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pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
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timestamp_add_now(TS_BEFORE_INITRAM);
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report_platform_info();
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if (CONFIG(INTEL_TXT))
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intel_txt_romstage_init();
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copy_spd(&pei_data, &spdi);
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sdram_initialize(&pei_data);
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timestamp_add_now(TS_AFTER_INITRAM);
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perform_raminit(s3resume);
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if (CONFIG(INTEL_TXT)) {
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printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n");
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@ -161,26 +59,8 @@ void mainboard_romstage_entry(void)
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txt_dump_regions();
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}
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post_code(0x3b);
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intel_early_me_status();
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int cbmem_was_initted = !cbmem_recovery(s3resume);
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if (s3resume && !cbmem_was_initted) {
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/* Failed S3 resume, reset to come up cleanly */
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printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
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system_reset();
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}
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/* Save data returned from MRC on non-S3 resumes. */
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if (!s3resume)
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save_mrc_data(&pei_data);
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haswell_unhide_peg();
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setup_sdram_meminfo(&pei_data);
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romstage_handoff_init(s3resume);
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mb_late_romstage_setup();
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