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mainboard/protectli/vault_cml: Switch to IT8784E 

The first platform samples came with IT8786E. The production units
switched to IT8784E in the final design.

Change the code to use IT8784E and reflect the proprietary firmware
configuration of the SIO chip.

TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74175
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Michał Żygowski 2023-04-03 13:25:17 +02:00 committed by Felix Singer
parent 6503474efe
commit d99de5db5b
5 changed files with 30 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/protectli/vault_cml/Kconfig
View File

@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_COMETLAKE_2 if BOARD_PROTECTLI_VP4630_VP4650
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPI_FLASH_MACRONIX
select SUPERIO_ITE_IT8786E
select SUPERIO_ITE_IT8784E
config MAINBOARD_DIR
default "protectli/vault_cml"

13
src/mainboard/protectli/vault_cml/acpi/superio.asl
View File

@ -1 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#undef SUPERIO_DEV
#undef SUPERIO_PNP_BASE
#undef IT8784E_SHOW_UARTA
#undef IT8784E_SHOW_UARTB
#undef IT8784E_SHOW_EC
#undef IT8784E_SHOW_KBC
#undef IT8784E_SHOW_PS2M
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x2e
#define IT8784E_SHOW_SP1
#define IT8784E_SHOW_EC
#include <superio/ite/it8784e/acpi/superio.asl>

8
src/mainboard/protectli/vault_cml/bootblock.c
View File

@ -3,18 +3,18 @@
#include <bootblock_common.h>
#include <soc/gpio.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8786e/it8786e.h>
#include <superio/ite/it8784e/it8784e.h>
#include "gpio.h"
#define UART_DEV PNP_DEV(0x2e, IT8786E_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO)
#define UART_DEV PNP_DEV(0x2e, IT8784E_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8784E_GPIO)
void bootblock_mainboard_early_init(void)
{
/* CLKIN freq 24MHz, Ext CLKIN for Watchdog, Internal VCC_OK */
ite_reg_write(GPIO_DEV, 0x23, 0x49);
/* Set pin native functions */
ite_reg_write(GPIO_DEV, 0x26, 0x00);
ite_reg_write(GPIO_DEV, 0x26, 0xf3);
/* Set GPIOS exposed on pin header as GPIO functions */
ite_reg_write(GPIO_DEV, 0x29, 0xc0);
/* External CLKIN PCICLK */

20
src/mainboard/protectli/vault_cml/devicetree.cb
View File

@ -192,17 +192,17 @@ chip soc/intel/cannonlake
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on
chip superio/ite/it8786e
register "TMPIN1.mode" = "THERMAL_PECI"
register "TMPIN1.offset" = "0x63"
chip superio/ite/it8784e
register "TMPIN1.mode" = "THERMAL_RESISTOR"
register "TMPIN2.mode" = "THERMAL_MODE_DISABLED"
register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
register "TMPIN3.mode" = "THERMAL_PECI"
register "TMPIN3.offset" = "0x63"
register "ec.vin_mask" = "VIN_ALL"
register "ec.smbus_24mhz" = "1"
register "ec.smbus_en" = "1"
# FAN1 is CPU fan (connector on board)
register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
register "FAN1.smart.tmpin" = " 1"
register "FAN1.smart.tmpin" = " 3"
register "FAN1.smart.tmp_off" = "40"
register "FAN1.smart.tmp_start" = "60"
register "FAN1.smart.tmp_full" = "85"
@ -215,24 +215,18 @@ chip soc/intel/cannonlake
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 on # COM 2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.2 on end # COM 2
device pnp 2e.3 off end # Printer Port
device pnp 2e.4 on # Environment Controller
io 0x60 = 0xa40
io 0x62 = 0xa30
irq 0x70 = 9
irq 0xf0 = 0x80 # clear 3VSB status
end
device pnp 2e.5 off end # Keyboard
device pnp 2e.6 off end # Mouse
device pnp 2e.7 off end # GPIO
device pnp 2e.8 off end # COM 3
device pnp 2e.9 off end # COM 4
device pnp 2e.a off end # CIR
device pnp 2e.b off end # COM 5
device pnp 2e.c off end # COM 6
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end

5
src/mainboard/protectli/vault_cml/dsdt.asl
View File

@ -21,5 +21,10 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
Scope (\_SB.PCI0.LPCB)
{
#include "acpi/superio.asl"
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
}