diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index e993ddbbf9..a9fd35e1b9 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,21 +17,33 @@ Scope (\_SB.PCI0) {
 	/* EMMC */
 	Device(PEMC) {
 		Name(_ADR, 0x001A0000)
+		Name (TEMP, 0)
 
 		OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
 		Field(SCSR, WordAcc, NoLock, Preserve) {
-			Offset(0xA2),   // 0xA2, Device PG config
+			Offset (0x84),	/* PMECTRLSTATUS */
+			PMCR, 16,
+			Offset (0xA2),	/* PG_CONFIG */
 			, 2,
-			PGEN, 1         // [BIT2] PGE - PG Enable
+			PGEN, 1,	/* PG_ENABLE */
 		}
 
 		Method(_PS0, 0, Serialized) {
-			Stall (50) // Sleep 50 ms
+			Stall (50) // Sleep 50 us
+
 			Store(0, PGEN) // Disable PG
+
+			/* Set Power State to D0 */
+			And (PMCR, 0xFFFC, PMCR)
+			Store (PMCR, ^TEMP)
 		}
 
 		Method(_PS3, 0, Serialized) {
 			Store(1, PGEN) // Enable PG
+
+			/* Set Power State to D3 */
+			Or (PMCR, 0x0003, PMCR)
+			Store (PMCR, ^TEMP)
 		}
 	}