From d9b1dfe96806bd1985c722fd52f7dbf83a960f0f Mon Sep 17 00:00:00 2001 From: Garmin Chang Date: Sun, 11 Sep 2022 21:12:16 +0800 Subject: [PATCH] soc/mediatek/mt8188: Fix some wrong settings for PLLs The observed CPU big core frequency is double compared with the current PLL setting. Therefore fix the wrong setting for PLL register APMIXED_ARMPLL_BL. Moreover, we also fix some wrong settings for other PLLs. TEST=CPU frequency of big core CPU is correct and bootup correctly. BUG=b:244215537 Signed-off-by: Garmin Chang Change-Id: I9126f439d7a5136b2fb8d66f103ef427a0b08a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67543 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8188/pll.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c index f7ce86b11c..735ff473ae 100644 --- a/src/soc/mediatek/mt8188/pll.c +++ b/src/soc/mediatek/mt8188/pll.c @@ -399,58 +399,58 @@ static const u32 pll_div_rate[] = { static const struct pll plls[] = { PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, - NO_RSTB_SHIFT, 22, armpll_ll_con0, 24, armpll_ll_con1, 0, + NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, pll_div_rate), PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con3, - NO_RSTB_SHIFT, 22, armpll_bl_con0, 24, armpll_bl_con1, 0, + NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0, pll_div_rate), PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, - NO_RSTB_SHIFT, 22, ccipll_con0, 24, ccipll_con1, 0, + NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, pll_div_rate), PLL(APMIXED_ETHPLL, ethpll_con0, ethpll_con3, - NO_RSTB_SHIFT, 22, ethpll_con0, 24, ethpll_con1, 0, + NO_RSTB_SHIFT, 22, ethpll_con1, 24, ethpll_con1, 0, pll_div_rate), PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, - NO_RSTB_SHIFT, 22, msdcpll_con0, 24, msdcpll_con1, 0, + NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, pll_div_rate), PLL(APMIXED_TVDPLL1, tvdpll1_con0, tvdpll1_con3, - NO_RSTB_SHIFT, 22, tvdpll1_con0, 24, tvdpll1_con1, 0, + NO_RSTB_SHIFT, 22, tvdpll1_con1, 24, tvdpll1_con1, 0, pll_div_rate), PLL(APMIXED_TVDPLL2, tvdpll2_con0, tvdpll2_con3, - NO_RSTB_SHIFT, 22, tvdpll2_con0, 24, tvdpll2_con1, 0, + NO_RSTB_SHIFT, 22, tvdpll2_con1, 24, tvdpll2_con1, 0, pll_div_rate), PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, - 23, 22, mmpll_con0, 24, mmpll_con1, 0, + 23, 22, mmpll_con1, 24, mmpll_con1, 0, pll_div_rate), PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, - 23, 22, mainpll_con0, 24, mainpll_con1, 0, + 23, 22, mainpll_con1, 24, mainpll_con1, 0, pll_div_rate), PLL(APMIXED_IMGPLL, imgpll_con0, imgpll_con3, - NO_RSTB_SHIFT, 22, imgpll_con0, 24, imgpll_con1, 0, + NO_RSTB_SHIFT, 22, imgpll_con1, 24, imgpll_con1, 0, pll_div_rate), PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con3, - 23, 22, univpll_con0, 24, univpll_con1, 0, + 23, 22, univpll_con1, 24, univpll_con1, 0, pll_div_rate), PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, - NO_RSTB_SHIFT, 22, adsppll_con0, 24, adsppll_con1, 0, + NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, pll_div_rate), PLL(APMIXED_APLL1, apll1_con0, apll1_con4, - NO_RSTB_SHIFT, 32, apll1_con0, 24, apll1_con2, 0, + NO_RSTB_SHIFT, 32, apll1_con2, 24, apll1_con2, 0, pll_div_rate), PLL(APMIXED_APLL2, apll2_con0, apll2_con4, - NO_RSTB_SHIFT, 32, apll2_con0, 24, apll2_con2, 0, + NO_RSTB_SHIFT, 32, apll2_con2, 24, apll2_con2, 0, pll_div_rate), PLL(APMIXED_APLL3, apll3_con0, apll3_con4, - NO_RSTB_SHIFT, 32, apll3_con0, 24, apll3_con2, 0, + NO_RSTB_SHIFT, 32, apll3_con2, 24, apll3_con2, 0, pll_div_rate), PLL(APMIXED_APLL4, apll4_con0, apll4_con4, - NO_RSTB_SHIFT, 32, apll4_con0, 24, apll4_con2, 0, + NO_RSTB_SHIFT, 32, apll4_con2, 24, apll4_con2, 0, pll_div_rate), PLL(APMIXED_APLL5, apll5_con0, apll5_con4, - NO_RSTB_SHIFT, 32, apll5_con0, 24, apll5_con2, 0, + NO_RSTB_SHIFT, 32, apll5_con2, 24, apll5_con2, 0, pll_div_rate), PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, - NO_RSTB_SHIFT, 22, mfgpll_con0, 24, mfgpll_con1, 0, + NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, pll_div_rate), };