mb/google/hatch/scout: update gpios and device tree
Scout-specific changes to puff reference following bring-up - copy baseline changes from genesis - update GPIOs - update PCIe ports for TPUs - remove LSPCON - enable eMMC - disable touch I2C - enable uart BUG=b:187078663 TEST=boot scout BRANCH=none Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Jeff Chase
Tim Wawrzynczak
parent
cf6e4570db
commit
d9b714dada
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@ -9,33 +9,83 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_A16, NONE, DEEP),
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/* A18 : LAN_PE_ISOLATE_ODL */
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PAD_CFG_GPO(GPP_A18, 1, DEEP),
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/* A19 : Not connected */
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PAD_NC(GPP_A19, NONE),
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/* A20 : Not connected */
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PAD_NC(GPP_A20, NONE),
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/* A23 : M2_WLAN_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
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/* B5 : LAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* B6 : M2_SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* B7 : M2_TPU0_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* B8 : CLK_PCIE_REQ3 (not connected) */
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PAD_NC(GPP_B8, NONE),
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/* B9 : M2_TPU1_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* B10 : M2_WLAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* C0 : SMBCLK */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* C1 : SMBDATA */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* C3 : PCH_MBCLK1_R (i350) */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* C4 : PCH_MBDAT1_R (i350) */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* C6: M2_WLAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
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/* C7 : LAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
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/* C10 : PCH_PCON_RST_ODL */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C11 : PCH_PCON_PDB_ODL */
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/* C11 : PCH_PCON1_PDB_ODL */
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PAD_CFG_GPO(GPP_C11, 1, DEEP),
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/* C12 : PCH_RX_TSUM_UART_TX */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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/* C13 : PCH_RX_TSUM_UART_RX */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* C15 : WLAN_OFF_L */
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PAD_CFG_GPO(GPP_C15, 1, DEEP),
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/* E2 : EN_PP_MST_OD */
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PAD_CFG_GPO(GPP_E2, 1, DEEP),
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/* E9 : USB_A0_OC_ODL */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/*
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* TODO(b/187094460): Re-enable touch screen I2C after resolving USB
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* conflict
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*/
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/* C18 : PCH_I2C_USI_SDA */
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PAD_NC(GPP_C18, NONE),
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/* C19 : PCH_I2C_USI_SDL */
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PAD_NC(GPP_C19, NONE),
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/* D13 : SMBUS_ISP_SCALAR */
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PAD_CFG_GPO(GPP_D13, 0, DEEP),
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/* D14 : EC_PCH_INT_L */
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PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT),
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/* D15 : USI_RST_L */
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PAD_CFG_GPO(GPP_D15, 1, DEEP),
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/* E2 : Not connected */
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PAD_NC(GPP_E2, NONE),
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/* E3 : TPU_RST_PIN40 */
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PAD_CFG_GPO(GPP_E3, 1, DEEP),
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/* E7 : TPU_RST_PIN42 */
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PAD_CFG_GPO(GPP_E7, 1, DEEP),
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/* E9 : PU 10K to PP3300_SOC_A */
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PAD_NC(GPP_E9, NONE),
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/* E10 : USB_A1_OC_ODL */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* E15 : PCH_TYPEC_UPFB */
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PAD_CFG_GPI(GPP_E15, NONE, DEEP),
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/* E18 : DDI1_CLK */
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PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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/* E19 : DDI1_DATA */
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PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
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/* F11 : EMMC_CMD */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
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@ -66,6 +116,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5: PCH_I2C_PCON_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H6 : PCH_I2C_TPU_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : PCH_I2C_TPU_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H22 : PWM_PP3300_BIOZZER */
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PAD_CFG_GPO(GPP_H22, 0, DEEP),
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};
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@ -5,4 +5,7 @@
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#include <baseboard/gpio.h>
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#undef EC_SYNC_IRQ
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#define EC_SYNC_IRQ GPP_D14_IRQ
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#endif
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@ -13,7 +13,7 @@ chip soc/intel/cannonlake
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[PchSerialIoIndexSPI1] = PchSerialIoPci,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoPci,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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@ -182,16 +182,49 @@ chip soc/intel/cannonlake
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},
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}"
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# PCIe port 7 for LAN
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# PCIe root port 7 for LAN
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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# PCIe port 11 (x2) for NVMe hybrid storage devices
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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# Uses CLK SRC 0
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register "PcieClkSrcUsage[0]" = "6"
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register "PcieClkSrcClkReq[0]" = "0"
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# PCIe root port 8 for WLAN
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register "PcieRpEnable[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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# Uses CLK SRC 3
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register "PcieClkSrcUsage[3]" = "7"
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register "PcieClkSrcClkReq[3]" = "3"
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# PCIe root port 9 for SSD (PCIe Lanes 9-12)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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# RP 9 uses CLK SRC 1
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register "PcieClkSrcUsage[1]" = "8"
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register "PcieClkSrcClkReq[1]" = "1"
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# PCIe root port 10-12 disabled
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register "PcieRpEnable[9]" = "0"
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register "PcieRpEnable[10]" = "0"
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register "PcieRpEnable[11]" = "0"
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# PCIe root port 13 TPU0
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register "PcieRpEnable[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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# RP 13 uses CLK SRC 2
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register "PcieClkSrcUsage[2]" = "12"
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register "PcieClkSrcClkReq[2]" = "2"
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# PCIe root port 14 TPU1
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register "PcieRpEnable[13]" = "1"
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register "PcieRpLtrEnable[13]" = "1"
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# RP 14 uses CLK SRC 4
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register "PcieClkSrcUsage[4]" = "13"
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register "PcieClkSrcClkReq[4]" = "4"
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register "PcieRpEnable[14]" = "0"
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register "PcieRpEnable[15]" = "0"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "vSD3_CD_B"
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@ -205,38 +238,35 @@ chip soc/intel/cannonlake
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chip drivers/intel/dptf
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## Active Policy
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register "policies.active[0]" = "{.target=DPTF_CPU,
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.thresholds={TEMP_PCT(90, 85),
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TEMP_PCT(85, 75),
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TEMP_PCT(80, 65),
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TEMP_PCT(75, 55),
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TEMP_PCT(70, 45),}}"
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.thresholds={TEMP_PCT(94, 0),}}"
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register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
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.thresholds={TEMP_PCT(50, 85),
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TEMP_PCT(47, 75),
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TEMP_PCT(45, 65),
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TEMP_PCT(42, 55),
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TEMP_PCT(39, 45),}}"
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.thresholds={TEMP_PCT(72, 90),
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TEMP_PCT(68, 80),
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TEMP_PCT(62, 70),
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TEMP_PCT(54, 60),
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TEMP_PCT(46, 50),
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TEMP_PCT(39, 40),}}"
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## Passive Policy
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register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)"
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register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
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register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
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register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)"
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## Critical Policy
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register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
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register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
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register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)"
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## Power Limits Control
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# PL1 is fixed at 15W, avg over 28-32s interval
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# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
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# 51-51W PL2 in 1000mW increments, avg over 28-32s interval
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register "controls.power_limits.pl1" = "{
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.min_power = 15000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,}"
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.granularity = 125,}"
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register "controls.power_limits.pl2" = "{
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.min_power = 25000,
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.max_power = 64000,
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.min_power = 51000,
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.max_power = 51000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,}"
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@ -333,15 +363,13 @@ chip soc/intel/cannonlake
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device usb 3.3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Rear Left""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 0)"
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device usb 3.4 on end
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# USB3 Port 5 is not populated
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device usb 3.4 off end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Rear Middle""
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register "desc" = ""USB3 M.2 HDMI-to-USB""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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register "group" = "ACPI_PLD_GROUP(2, 0)"
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device usb 3.5 on end
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end
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end
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@ -351,22 +379,9 @@ chip soc/intel/cannonlake
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# RFU - Reserved for Future Use.
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end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 on
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chip drivers/i2c/generic
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register "hid" = ""1AF80175""
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register "name" = ""PS17""
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register "desc" = ""Parade PS175""
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device i2c 4a on end
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end
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end # I2C #2, PCON PS175.
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device pci 15.3 on
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chip drivers/i2c/generic
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register "hid" = ""10EC2142""
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register "name" = ""RTD2""
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register "desc" = ""Realtek RTD2142""
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device i2c 4a on end
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end
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end # I2C #3, Realtek RTD2142.
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device pci 15.2 off end # I2C #2, PCON PS175.
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device pci 15.3 off end # I2C #3, Realtek RTD2142.
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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@ -381,9 +396,9 @@ chip soc/intel/cannonlake
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device i2c 1a on end
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end
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end #I2C #4
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device pci 1a.0 on end # eMMC
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device pci 1c.6 on
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chip drivers/net
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device pci 1a.0 on end # eMMC
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device pci 1c.6 on # PCI Root Port 7 (LAN)
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chip drivers/net # RTL8111H Ethernet NIC
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register "customized_leds" = "0x05af"
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register "wake" = "GPE0_DW1_07" # GPP_C7
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
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@ -393,8 +408,26 @@ chip soc/intel/cannonlake
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register "device_index" = "0"
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device pci 00.0 on end
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end
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end # RTL8111H Ethernet NIC
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device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
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end
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device pci 1c.7 on # PCI Root Port 8 (WLAN)
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register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
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end
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device pci 1d.0 on # PCI Root Port 9 (SSD)
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register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
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end
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device pci 1d.1 off end # PCI Root Port 10 (Not connected)
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device pci 1d.2 off end # PCI Root Port 11 (Not connected)
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device pci 1d.3 off end # PCI Root Port 12 (Not connected)
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device pci 1d.4 on # PCI Root Port 13 (TPU0)
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register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot
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end
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device pci 1d.5 on # PCI Root Port 14 (TPU1)
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register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot
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end
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device pci 1d.6 on end # PCI Root Port 15 (non-root)
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device pci 1d.7 on end # PCI Root Port 16 (non-root)
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device pci 1e.0 on end # UART #0
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device pci 1e.1 on end # UART #1
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device pci 1e.3 off end # GSPI #1
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end
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