First attempt to clean up SPI probing and create a common
construct: the flash bus. At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
e16d43c041
commit
d9b7ae8bec
5 changed files with 211 additions and 126 deletions
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@ -35,6 +35,17 @@
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#include <unistd.h>
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#include "flash.h"
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/**
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* flashrom defaults to LPC flash devices. If a known SPI controller is found
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* and the SPI strappings are set, this will be overwritten by the probing code.
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*
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* Eventually, this will become an array when multiple flash support works.
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*/
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flashbus_t flashbus = BUS_TYPE_LPC;
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void *spibar = NULL;
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static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
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{
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uint8_t tmp;
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@ -124,7 +135,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
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* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
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* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
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*/
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new = old | 0x2c4;
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new = old | 0x02c4;
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if (new == old)
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return 0;
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@ -185,88 +196,131 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
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return enable_flash_ich(dev, name, 0xdc);
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}
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void *ich_spibar = NULL;
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#define ICH_STRAP_RSVD 0x00
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#define ICH_STRAP_SPI 0x01
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#define ICH_STRAP_PCI 0x02
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#define ICH_STRAP_LPC 0x03
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static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) {
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uint32_t mmio_base;
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mmio_base = (pci_read_long(dev, 0xbc)) << 8;
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printf_debug("MMIO base at = 0x%x\n", mmio_base);
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ich_spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
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spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
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fd_mem, mmio_base);
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if (ich_spibar == MAP_FAILED) {
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if (spibar == MAP_FAILED) {
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perror("Can't mmap memory using " MEM_DEV);
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exit(1);
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}
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printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(ich_spibar + 0x6c));
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viaspi_detected = 1;
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printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(spibar + 0x6c));
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flashbus = BUS_TYPE_VIA_SPI;
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return 0;
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}
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static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar)
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static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation)
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{
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int ret, i;
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uint8_t old, new, bbs, buc;
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uint16_t spibar_offset;
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uint32_t tmp, gcs;
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void *rcrb;
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static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
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/* Enable Flash Writes */
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ret = enable_flash_ich_dc(dev, name);
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/* Read the Root Complex Base Address Register (RCBA) */
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tmp = pci_read_long(dev, 0xf0);
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/* Calculate the Root Complex Register Block address */
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tmp &= 0xffffc000;
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/* Get physical address of Root Complex Register Block */
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tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
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printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
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/* Map RCBA to virtual memory */
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rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp);
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if (rcrb == MAP_FAILED) {
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perror("Can't mmap memory using " MEM_DEV);
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exit(1);
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}
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printf_debug("GCS address = 0x%x\n", tmp + 0x3410);
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gcs = *(volatile uint32_t *)(rcrb + 0x3410);
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printf_debug("GCS = 0x%x: ", gcs);
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printf_debug("BIOS Interface Lock-Down: %sabled, ",
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(gcs & 0x1) ? "en" : "dis");
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bbs = (gcs >> 10) & 0x3;
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printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs,
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(bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
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if (bbs >= 2)
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ich7_detected = 0;
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printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
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buc = *(volatile uint8_t *)(rcrb + 0x3414);
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printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled");
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/* It seems the ICH7 does not support SPI and LPC chips at the same
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* time. At least not with our current code. So we prevent searching
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* on ICH7 when the southbridge is strapped to LPC
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*/
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if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
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/* No further SPI initialization required */
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return ret;
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}
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switch (ich_generation) {
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case 7:
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flashbus = BUS_TYPE_ICH7_SPI;
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spibar_offset = 0x3020;
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break;
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case 8:
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flashbus = BUS_TYPE_ICH9_SPI;
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spibar_offset = 0x3020;
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break;
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case 9:
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default: /* Future version might behave the same */
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flashbus = BUS_TYPE_ICH9_SPI;
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spibar_offset = 0x3800;
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break;
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}
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/* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
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printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, (uint16_t)spibar);
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printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
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// Assign Virtual Address
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ich_spibar = rcrb + spibar;
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/* Assign Virtual Address */
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spibar = rcrb + spibar_offset;
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if (ich7_detected) {
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int i;
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printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(ich_spibar + 0));
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printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(ich_spibar + 2));
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printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(ich_spibar + 4));
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switch (flashbus) {
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case BUS_TYPE_ICH7_SPI:
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printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(spibar + 0));
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printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(spibar + 2));
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printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(spibar + 4));
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for (i=0; i < 8; i++) {
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int offs;
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offs = 8 + (i * 8);
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printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
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printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(ich_spibar + offs +4), i);
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printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(spibar + offs), i);
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printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(spibar + offs +4), i);
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}
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printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(ich_spibar + 0x50));
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printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(ich_spibar + 0x54));
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printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(ich_spibar + 0x56));
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printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(ich_spibar + 0x58));
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printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(ich_spibar + 0x5c));
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printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(spibar + 0x50));
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printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(spibar + 0x54));
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printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(spibar + 0x56));
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printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(spibar + 0x58));
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printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(spibar + 0x5c));
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for (i=0; i < 4; i++) {
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int offs;
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offs = 0x60 + (i * 4);
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printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
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printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(spibar + offs), i);
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}
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printf_debug("\n");
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if ( (*(uint16_t *)ich_spibar) & (1 << 15)) {
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if ( (*(uint16_t *)spibar) & (1 << 15)) {
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printf("WARNING: SPI Configuration Lockdown activated.\n");
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}
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break;
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case BUS_TYPE_ICH9_SPI:
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/* TODO: Add dumping function for ICH8/ICH9, or drop the
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* whole SPIBAR dumping from chipset_enable.c - There's
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* inteltool for this task already.
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*/
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break;
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default:
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/* Nothing */
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break;
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}
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old = pci_read_byte(dev, 0xdc);
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@ -277,38 +331,30 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsign
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case 1:
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case 2:
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printf_debug("prefetching %sabled, caching %sabled, ",
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(new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en");
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(new & 0x2) ? "en" : "dis",
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(new & 0x1) ? "dis" : "en");
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break;
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default:
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printf_debug("invalid prefetching/caching settings, ");
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break;
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}
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return enable_flash_ich_dc(dev, name);
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}
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/* Flag for ICH7 SPI register block */
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int ich7_detected = 0;
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int viaspi_detected = 0;
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return ret;
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}
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static int enable_flash_ich7(struct pci_dev *dev, const char *name)
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{
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ich7_detected = 1;
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return enable_flash_ich_dc_spi(dev, name, 0x3020);
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return enable_flash_ich_dc_spi(dev, name, 7);
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}
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/* Flag for ICH8/ICH9 SPI register block */
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int ich9_detected = 0;
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static int enable_flash_ich8(struct pci_dev *dev, const char *name)
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{
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ich9_detected = 1;
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return enable_flash_ich_dc_spi(dev, name, 0x3020);
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return enable_flash_ich_dc_spi(dev, name, 8);
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}
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static int enable_flash_ich9(struct pci_dev *dev, const char *name)
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{
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ich9_detected = 1;
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return enable_flash_ich_dc_spi(dev, name, 0x3800);
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return enable_flash_ich_dc_spi(dev, name, 9);
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}
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static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
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@ -370,10 +370,17 @@ void print_supported_boards(void);
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/* chipset_enable.c */
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int chipset_flash_enable(void);
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void print_supported_chipsets(void);
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extern int ich7_detected;
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extern int viaspi_detected;
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extern int ich9_detected;
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extern void *ich_spibar;
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typedef enum {
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BUS_TYPE_LPC,
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BUS_TYPE_ICH7_SPI,
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BUS_TYPE_ICH9_SPI,
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BUS_TYPE_IT87XX_SPI,
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BUS_TYPE_VIA_SPI
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} flashbus_t;
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extern flashbus_t flashbus;
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extern void *spibar;
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/* Physical memory mapping device */
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#if defined (__sun) && (defined(__i386) || defined(__amd64))
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@ -131,20 +131,20 @@ static OPCODES *curopcodes = NULL;
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static inline uint32_t REGREAD32(int X)
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{
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volatile uint32_t regval;
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regval = *(volatile uint32_t *) ((uint8_t *) ich_spibar + X);
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regval = *(volatile uint32_t *) ((uint8_t *) spibar + X);
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return regval;
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}
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static inline uint16_t REGREAD16(int X)
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{
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volatile uint16_t regval;
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regval = *(volatile uint16_t *) ((uint8_t *) ich_spibar + X);
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regval = *(volatile uint16_t *) ((uint8_t *) spibar + X);
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return regval;
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}
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#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)ich_spibar+X)=Y)
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#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)ich_spibar+X)=Y)
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#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)ich_spibar+X)=Y)
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#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y)
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#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y)
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#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y)
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/* Common SPI functions */
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static int program_opcodes(OPCODES * op);
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@ -175,58 +175,51 @@ OPCODES O_ST_M25P = {
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int program_opcodes(OPCODES * op)
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{
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uint8_t a;
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uint16_t temp16;
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uint32_t temp32;
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uint16_t preop, optype;
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uint32_t opmenu[2];
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/* Program Prefix Opcodes */
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temp16 = 0;
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preop = 0;
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/* 0:7 Prefix Opcode 1 */
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temp16 = (op->preop[0]);
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preop = (op->preop[0]);
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/* 8:16 Prefix Opcode 2 */
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temp16 |= ((uint16_t) op->preop[1]) << 8;
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if ((ich7_detected) || (viaspi_detected)) {
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REGWRITE16(ICH7_REG_PREOP, temp16);
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} else if (ich9_detected) {
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REGWRITE16(ICH9_REG_PREOP, temp16);
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}
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preop |= ((uint16_t) op->preop[1]) << 8;
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/* Program Opcode Types 0 - 7 */
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temp16 = 0;
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optype = 0;
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for (a = 0; a < 8; a++) {
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temp16 |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
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optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
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}
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if ((ich7_detected) || (viaspi_detected)) {
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REGWRITE16(ICH7_REG_OPTYPE, temp16);
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} else if (ich9_detected) {
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REGWRITE16(ICH9_REG_OPTYPE, temp16);
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}
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/* Program Allowable Opcodes 0 - 3 */
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temp32 = 0;
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opmenu[0] = 0;
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for (a = 0; a < 4; a++) {
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temp32 |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
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opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
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}
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if ((ich7_detected) || (viaspi_detected)) {
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REGWRITE32(ICH7_REG_OPMENU, temp32);
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} else if (ich9_detected) {
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REGWRITE32(ICH9_REG_OPMENU, temp32);
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}
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/*Program Allowable Opcodes 4 - 7 */
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temp32 = 0;
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opmenu[1] = 0;
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for (a = 4; a < 8; a++) {
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temp32 |=
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((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
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opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
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}
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if ((ich7_detected) || (viaspi_detected)) {
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REGWRITE32(ICH7_REG_OPMENU + 4, temp32);
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} else if (ich9_detected) {
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REGWRITE32(ICH9_REG_OPMENU + 4, temp32);
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switch (flashbus) {
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case BUS_TYPE_ICH7_SPI:
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case BUS_TYPE_VIA_SPI:
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REGWRITE16(ICH7_REG_PREOP, preop);
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REGWRITE16(ICH7_REG_OPTYPE, optype);
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REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
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REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
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break;
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case BUS_TYPE_ICH9_SPI:
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REGWRITE16(ICH9_REG_PREOP, preop);
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REGWRITE16(ICH9_REG_OPTYPE, optype);
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REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
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REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
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break;
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default:
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printf_debug("%s: unsupported chipset\n", __FUNCTION__);
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return -1;
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}
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return 0;
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@ -340,6 +333,7 @@ static int ich9_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
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uint8_t datalength, uint8_t * data)
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{
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int write_cmd = 0;
|
||||
int timeout;
|
||||
uint32_t temp32;
|
||||
uint32_t a;
|
||||
|
||||
|
|
@ -410,9 +404,12 @@ static int ich9_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
|
|||
REGWRITE32(ICH9_REG_SSFS, temp32);
|
||||
|
||||
/*wait for cycle complete */
|
||||
while ((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) {
|
||||
/*TODO; Do something that this can't lead into an endless loop. but some
|
||||
* commands may cause this to be last more than 30 seconds */
|
||||
timeout = 1000 * 60; // 60s is a looong timeout.
|
||||
while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
|
||||
myusec_delay(1000);
|
||||
}
|
||||
if (!timeout) {
|
||||
printf_debug("timeout\n");
|
||||
}
|
||||
|
||||
if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
|
||||
|
|
@ -438,12 +435,16 @@ static int ich9_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
|
|||
static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
|
||||
uint8_t datalength, uint8_t * data)
|
||||
{
|
||||
if (ich7_detected)
|
||||
return ich7_run_opcode(nr, op, offset, datalength, data, 64);
|
||||
else if (viaspi_detected)
|
||||
switch (flashbus) {
|
||||
case BUS_TYPE_VIA_SPI:
|
||||
return ich7_run_opcode(nr, op, offset, datalength, data, 16);
|
||||
else if (ich9_detected)
|
||||
case BUS_TYPE_ICH7_SPI:
|
||||
return ich7_run_opcode(nr, op, offset, datalength, data, 64);
|
||||
case BUS_TYPE_ICH9_SPI:
|
||||
return ich9_run_opcode(nr, op, offset, datalength, data);
|
||||
default:
|
||||
printf_debug("%s: unsupported chipset\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
/* If we ever get here, something really weird happened */
|
||||
return -1;
|
||||
|
|
@ -541,7 +542,7 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf)
|
|||
int page_size = flash->page_size;
|
||||
int maxdata = 64;
|
||||
|
||||
if (viaspi_detected) {
|
||||
if (flashbus == BUS_TYPE_VIA_SPI) {
|
||||
maxdata = 16;
|
||||
}
|
||||
|
||||
|
|
@ -572,7 +573,7 @@ int ich_spi_write(struct flashchip *flash, uint8_t * buf)
|
|||
break;
|
||||
}
|
||||
|
||||
if (viaspi_detected) {
|
||||
if (flashbus == BUS_TYPE_VIA_SPI) {
|
||||
maxdata = 16;
|
||||
}
|
||||
for (j = 0; j < erase_size / page_size; j++) {
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
*
|
||||
* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
|
||||
* Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
|
||||
* Copyright (C) 2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -112,8 +113,13 @@ static uint16_t find_ite_spi_flash_port(uint16_t port)
|
|||
int it87xx_probe_spi_flash(const char *name)
|
||||
{
|
||||
it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1);
|
||||
|
||||
if (!it8716f_flashport)
|
||||
it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
|
||||
|
||||
if (it8716f_flashport)
|
||||
flashbus = BUS_TYPE_IT87XX_SPI;
|
||||
|
||||
return (!it8716f_flashport);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -34,13 +34,16 @@ void spi_prettyprint_status_register(struct flashchip *flash);
|
|||
|
||||
int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
|
||||
{
|
||||
if (it8716f_flashport)
|
||||
switch (flashbus) {
|
||||
case BUS_TYPE_IT87XX_SPI:
|
||||
return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
else if ((ich7_detected) || (viaspi_detected))
|
||||
return ich_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
case BUS_TYPE_ICH7_SPI:
|
||||
case BUS_TYPE_ICH9_SPI:
|
||||
case BUS_TYPE_VIA_SPI:
|
||||
return ich_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
default:
|
||||
printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -135,9 +138,16 @@ int probe_spi_rdid(struct flashchip *flash) {
|
|||
int probe_spi_rdid4(struct flashchip *flash) {
|
||||
|
||||
/* only some SPI chipsets support 4 bytes commands */
|
||||
if (!((ich7_detected) || (ich9_detected) || (viaspi_detected)))
|
||||
return 0;
|
||||
return probe_spi_rdid_generic(flash, 4);
|
||||
switch (flashbus) {
|
||||
case BUS_TYPE_ICH7_SPI:
|
||||
case BUS_TYPE_ICH9_SPI:
|
||||
case BUS_TYPE_VIA_SPI:
|
||||
return probe_spi_rdid_generic(flash, 4);
|
||||
default:
|
||||
printf_debug("4b ID not supported on this SPI controller\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int probe_spi_res(struct flashchip *flash)
|
||||
|
|
@ -316,11 +326,17 @@ int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
|
|||
|
||||
void spi_page_program(int block, uint8_t *buf, uint8_t *bios)
|
||||
{
|
||||
if (it8716f_flashport) {
|
||||
switch (flashbus) {
|
||||
case BUS_TYPE_IT87XX_SPI:
|
||||
it8716f_spi_page_program(block, buf, bios);
|
||||
return;
|
||||
break;
|
||||
case BUS_TYPE_ICH7_SPI:
|
||||
case BUS_TYPE_ICH9_SPI:
|
||||
printf_debug("%s called, but not implemented for ICH\n", __FUNCTION__);
|
||||
break;
|
||||
default:
|
||||
printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
|
||||
}
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -375,25 +391,34 @@ void spi_nbyte_read(int address, uint8_t *bytes, int len)
|
|||
|
||||
int spi_chip_read(struct flashchip *flash, uint8_t *buf)
|
||||
{
|
||||
if (it8716f_flashport)
|
||||
|
||||
switch (flashbus) {
|
||||
case BUS_TYPE_IT87XX_SPI:
|
||||
return it8716f_spi_chip_read(flash, buf);
|
||||
else if ((ich7_detected) || (viaspi_detected))
|
||||
case BUS_TYPE_ICH7_SPI:
|
||||
case BUS_TYPE_ICH9_SPI:
|
||||
case BUS_TYPE_VIA_SPI:
|
||||
return ich_spi_read(flash, buf);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_read(flash, buf);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
default:
|
||||
printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int spi_chip_write(struct flashchip *flash, uint8_t *buf)
|
||||
{
|
||||
if (it8716f_flashport)
|
||||
switch (flashbus) {
|
||||
case BUS_TYPE_IT87XX_SPI:
|
||||
return it8716f_spi_chip_write(flash, buf);
|
||||
else if ((ich7_detected) || (viaspi_detected))
|
||||
case BUS_TYPE_ICH7_SPI:
|
||||
case BUS_TYPE_ICH9_SPI:
|
||||
case BUS_TYPE_VIA_SPI:
|
||||
return ich_spi_write(flash, buf);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_write(flash, buf);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
default:
|
||||
printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue