broadwell boards: Use Haswell hostbridge.asl
Use hostbridge.asl from Haswell instead of Broadwell. Both files are equivalent. Then, drop the now-unused hostbridge.asl from Broadwell. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
Patrick Georgi
parent
74fdd1a5b2
commit
d9cf794df4
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@ -25,7 +25,7 @@ DefinitionBlock(
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/broadwell/acpi/hostbridge.asl>
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#include <northbridge/intel/haswell/acpi/hostbridge.asl>
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#include <soc/intel/broadwell/pch/acpi/pch.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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}
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@ -26,7 +26,7 @@ DefinitionBlock(
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/broadwell/acpi/hostbridge.asl>
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#include <northbridge/intel/haswell/acpi/hostbridge.asl>
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#include <soc/intel/broadwell/pch/acpi/pch.asl>
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}
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}
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@ -26,7 +26,7 @@ DefinitionBlock(
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/broadwell/acpi/hostbridge.asl>
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#include <northbridge/intel/haswell/acpi/hostbridge.asl>
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#include <soc/intel/broadwell/pch/acpi/pch.asl>
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}
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}
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@ -22,7 +22,7 @@ DefinitionBlock(
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/broadwell/acpi/hostbridge.asl>
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#include <northbridge/intel/haswell/acpi/hostbridge.asl>
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#include <soc/intel/broadwell/pch/acpi/pch.asl>
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}
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}
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@ -1,200 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/iomap.h>
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Name (_HID, EISAID ("PNP0A08")) // PCIe
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Name (_CID, EISAID ("PNP0A03")) // PCI
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Name (_BBN, 0)
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Device (MCHC)
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{
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Name (_ADR, 0x00000000) // 0:0.0
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OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
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Field (MCHP, DWordAcc, NoLock, Preserve)
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{
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Offset (0x70), // ME Base Address
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MEBA, 64,
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Offset (0xa0), // Top of Used Memory
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TOM, 64,
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Offset (0xbc), // Top of Low Used Memory
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TLUD, 32,
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}
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}
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// Current Resource Settings
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Name (MCRS, ResourceTemplate()
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{
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// Bus Numbers
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
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// IO Region 0
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
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// PCI Config Space
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Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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// IO Region 1
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
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// VGA memory (0xa0000-0xbffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
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0x00020000,,, ASEG)
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// OPROM reserved (0xc0000-0xc3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
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0x00004000,,, OPR0)
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// OPROM reserved (0xc4000-0xc7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
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0x00004000,,, OPR1)
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// OPROM reserved (0xc8000-0xcbfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
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0x00004000,,, OPR2)
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// OPROM reserved (0xcc000-0xcffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
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0x00004000,,, OPR3)
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// OPROM reserved (0xd0000-0xd3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
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0x00004000,,, OPR4)
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// OPROM reserved (0xd4000-0xd7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
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0x00004000,,, OPR5)
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// OPROM reserved (0xd8000-0xdbfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
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0x00004000,,, OPR6)
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// OPROM reserved (0xdc000-0xdffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
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0x00004000,,, OPR7)
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// BIOS Extension (0xe0000-0xe3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
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0x00004000,,, ESG0)
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// BIOS Extension (0xe4000-0xe7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
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0x00004000,,, ESG1)
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// BIOS Extension (0xe8000-0xebfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
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0x00004000,,, ESG2)
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// BIOS Extension (0xec000-0xeffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ec000, 0x000effff, 0x00000000,
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0x00004000,,, ESG3)
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// System BIOS (0xf0000-0xfffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
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0x00010000,,, FSEG)
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// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000,,, PM01)
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// TPM Area (0xfed40000-0xfed44fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
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0x00005000,,, TPMR)
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})
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Method (_CRS, 0, Serialized)
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{
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// Find PCI resource area in MCRS
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CreateDwordField (MCRS, ^PM01._MIN, PMIN)
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CreateDwordField (MCRS, ^PM01._MAX, PMAX)
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CreateDwordField (MCRS, ^PM01._LEN, PLEN)
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// Fix up PCI memory region
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// Start with Top of Lower Usable DRAM
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// Lower 20 bits of TOLUD register need to be masked since they contain lock and
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// reserved bits.
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Local0 = ^MCHC.TLUD & (0xfff << 20)
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Local1 = ^MCHC.MEBA
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// Check if ME base is equal
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If (Local0 == Local1) {
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// Use Top Of Memory instead
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// Lower 20 bits of TOM register need to be masked since they contain lock and
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// reserved bits.
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Local0 = ^MCHC.TOM & (0x7ffff << 20)
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}
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PMIN = Local0
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PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
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PLEN = (PMAX - PMIN) + 1
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Return (MCRS)
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}
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/* PCI Device Resource Consumption */
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Device (PDRC)
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{
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 1)
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Name (PDRS, ResourceTemplate() {
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Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
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Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
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Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
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Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
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Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
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Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
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Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
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Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
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Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
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Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
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})
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// Current Resource Settings
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Method (_CRS, 0, Serialized)
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{
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Return (PDRS)
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}
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}
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/* Configurable TDP */
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#include <northbridge/intel/haswell/acpi/ctdp.asl>
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/* Integrated graphics 0:2.0 */
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#include <drivers/intel/gma/acpi/gfx.asl>
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