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soc/intel/cnl: Enable HECI3 depending on devicetree 

Currently HECI3 gets enabled by the option Heci3Enabled, but this
duplicates the devicetree on/off options. Therefore depend on the
devicetree for enablement of the HECI3 controller.

All corresponding mainboards were checked if the devicetree
configuration matches the Heci3Enabled setting, and divergent
devicetrees were adjusted.

Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2020-08-19 14:13:15 +02:00 committed by Michael Niewöhner
parent 5127cb8b16
commit d9e459428d
5 changed files with 5 additions and 9 deletions
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2
src/mainboard/prodrive/hermes/devicetree.cb
View File

@ -28,7 +28,7 @@ chip soc/intel/cannonlake
register "HeciEnabled" = "1"
end
device pci 16.1 on end # Management Engine Interface 2
device pci 16.4 on end # Management Engine Interface 3
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on end # SATA
device pci 1d.6 on # PCIe root port 15
device pci 00.0 on # Aspeed PCI Bridge

4
src/mainboard/purism/librem_whl/devicetree.cb
View File

@ -277,9 +277,7 @@ chip soc/intel/cannonlake
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off # Management Engine Interface 3
register "Heci3Enabled" = "0"
end
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on end # SATA
device pci 19.0 off end # I2C #4

4
src/mainboard/system76/lemp9/devicetree.cb
View File

@ -201,9 +201,7 @@ chip soc/intel/cannonlake
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off # Management Engine Interface 3
register "Heci3Enabled" = "0"
end
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on end # SATA
device pci 19.0 off end # I2C #4

1
src/soc/intel/cannonlake/chip.h
View File

@ -228,7 +228,6 @@ struct soc_intel_cannonlake_config {
uint8_t PchIshEnable;
/* Heci related */
uint8_t Heci3Enabled;
uint8_t DisableHeciRetry;
/* Gfx related */

3
src/soc/intel/cannonlake/fsp_params.c
View File

@ -525,7 +525,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
else
params->ScsUfsEnabled = dev->enabled;
params->Heci3Enabled = config->Heci3Enabled;
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
params->Heci3Enabled = is_dev_enabled(dev);
#if !CONFIG(HECI_DISABLE_USING_SMM)
dev = pcidev_path_on_root(PCH_DEVFN_CSE);
params->Heci1Disabled = !is_dev_enabled(dev);