diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 9ecbe95b41..bf77763954 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -69,21 +69,25 @@ static void adsp_init(struct device *dev)
 
 	/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
 	tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
-	if (config->adsp_d3_pg_disable) {
-		if (pch_is_wpt()) {
-			tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
-			tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+	if (pch_is_wpt()) {
+		if (config->adsp_d3_pg_enable) {
+			tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
+			if (config->adsp_sram_pg_enable)
+				tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+			else
+				tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
 		} else {
-			tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
-			tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+			tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
 		}
 	} else {
-		if (pch_is_wpt()) {
-			tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
-			tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
-		} else {
+		if (config->adsp_d3_pg_enable) {
 			tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
-			tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+			if (config->adsp_sram_pg_enable)
+				tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+			else
+				tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+		} else {
+			tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
 		}
 	}
 	pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 005ab36551..703c865a8f 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -84,8 +84,9 @@ struct soc_intel_broadwell_config {
 	uint8_t sio_i2c0_voltage;
 	uint8_t sio_i2c1_voltage;
 
-	/* Disable ADSP power gating in D3 */
-	uint8_t adsp_d3_pg_disable;
+	/* Enable ADSP power gating features */
+	uint8_t adsp_d3_pg_enable;
+	uint8_t adsp_sram_pg_enable;
 
 	/*
 	 * Clock Disable Map: