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arch/riscv: Delegate exceptions to supervisor mode if appropriate 

Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16160
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Jonathan Neuschäfer 2016-08-22 19:37:15 +02:00 committed by Martin Roth
parent 538e44683b
commit d9ff75f2cb
1 changed files with 10 additions and 0 deletions
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10
src/arch/riscv/virtual_memory.c
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@ -208,4 +208,14 @@ void mstatus_init(void)
clear_csr(mip, MIP_MSIP);
set_csr(mie, MIP_MSIP);
/* Configure which exception causes are delegated to supervisor mode */
set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH)
| (1 << CAUSE_FAULT_FETCH)
| (1 << CAUSE_ILLEGAL_INSTRUCTION)
| (1 << CAUSE_BREAKPOINT)
| (1 << CAUSE_FAULT_LOAD)
| (1 << CAUSE_FAULT_STORE)
| (1 << CAUSE_USER_ECALL)
);
}