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soc/amd/cezanne: introduce and use pstate_msr bitfield struct 

Add the pstate_msr union of a bitfield struct and a raw uint64_t to
allow easier access of the bitfields of the P state MSRs and use this
bitfield struct in get_pstate_core_freq and get_pstate_core_power. The
signature of those two function will be changed in a follow-up commit.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If92a4773c669ac2df45396eee52f6de780adbdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2023-03-10 00:00:47 +01:00
parent 659e154d68
commit da02a82f22
2 changed files with 24 additions and 19 deletions
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20
src/soc/amd/cezanne/acpi.c
View File

@ -99,13 +99,15 @@ uint32_t get_pstate_core_freq(msr_t pstate_def)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
union pstate_msr pstate_reg;
pstate_reg.raw = pstate_def.raw;
/* Core frequency multiplier */
core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK;
core_freq_mul = pstate_reg.cpu_fid_0_7;
/* Core frequency divisor ID */
core_freq_div =
(pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT;
core_freq_div = pstate_reg.cpu_dfs_id;
if (core_freq_div == 0) {
return 0;
@ -136,18 +138,18 @@ uint32_t get_pstate_core_freq(msr_t pstate_def)
uint32_t get_pstate_core_power(msr_t pstate_def)
{
uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
union pstate_msr pstate_reg;
pstate_reg.raw = pstate_def.raw;
/* Core voltage ID */
core_vid =
(pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT;
core_vid = pstate_reg.cpu_vid_0_7;
/* Current value in amps */
current_value_amps =
(pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT;
current_value_amps = pstate_reg.idd_value;
/* Current divisor */
current_divisor =
(pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT;
current_divisor = pstate_reg.idd_div;
/* Voltage */
if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) {

23
src/soc/amd/cezanne/include/soc/msr.h
View File

@ -4,19 +4,22 @@
#define AMD_CEZANNE_MSR_H
/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
#define PSTATE_DEF_LO_CUR_DIV_SHIFT 30
#define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT)
#define PSTATE_DEF_LO_CUR_VAL_SHIFT 22
#define PSTATE_DEF_LO_CUR_VAL_MASK (0xFF << PSTATE_DEF_LO_CUR_VAL_SHIFT)
#define PSTATE_DEF_LO_CORE_VID_SHIFT 14
#define PSTATE_DEF_LO_CORE_VID_MASK (0xFF << PSTATE_DEF_LO_CORE_VID_SHIFT)
#define PSTATE_DEF_LO_FREQ_DIV_SHIFT 8
#define PSTATE_DEF_LO_FREQ_DIV_MASK (0x3F << PSTATE_DEF_LO_FREQ_DIV_SHIFT)
union pstate_msr {
struct {
uint64_t cpu_fid_0_7 : 8; /* [ 0.. 7] */
uint64_t cpu_dfs_id : 6; /* [ 8..13] */
uint64_t cpu_vid_0_7 : 8; /* [14..21] */
uint64_t idd_value : 8; /* [22..29] */
uint64_t idd_div : 2; /* [30..31] */
uint64_t : 31; /* [32..62] */
uint64_t pstate_en : 1; /* [63..63] */
};
uint64_t raw;
};
#define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8
#define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A
#define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E
#define PSTATE_DEF_LO_FREQ_MUL_SHIFT 0
#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */