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Added support to ICH9 chipset family 

Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Anton Kochkov 2010-05-30 12:33:12 +00:00 committed by Stefan Reinauer
parent 32e6e411ea
commit da0b456ad0
7 changed files with 149 additions and 25 deletions
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28
util/inteltool/gpio.c
View File

@ -114,6 +114,24 @@ static const io_register_t ich8_gpio_registers[] = {
{ 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" } { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
}; };
static const io_register_t ich9_gpio_registers[] = {
{ 0x00, 4, "GPIO_USE_SEL" },
{ 0x04, 4, "GP_IO_SEL" },
{ 0x08, 4, "RESERVED" },
{ 0x0c, 4, "GP_LVL" },
{ 0x10, 4, "RESERVED" },
{ 0x14, 4, "RESERVED" },
{ 0x18, 4, "GPO_BLINK" },
{ 0x1c, 4, "GP_SER_BLINK" },
{ 0x20, 4, "GP_SB_CMDSTS" },
{ 0x24, 4, "GP_SB_DATA" },
{ 0x28, 4, "RESERVED" },
{ 0x2c, 4, "GPI_INV" },
{ 0x30, 4, "GPIO_USE_SEL2" },
{ 0x34, 4, "GP_IO_SEL2" },
{ 0x38, 4, "GP_LVL2" },
{ 0x3C, 4, "RESERVED" }
};
int print_gpios(struct pci_dev *sb) int print_gpios(struct pci_dev *sb)
{ {
@ -124,6 +142,16 @@ int print_gpios(struct pci_dev *sb)
printf("\n============= GPIOS =============\n\n"); printf("\n============= GPIOS =============\n\n");
switch (sb->device_id) { switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_ICH9DH:
case PCI_DEVICE_ID_INTEL_ICH9DO:
case PCI_DEVICE_ID_INTEL_ICH9R:
case PCI_DEVICE_ID_INTEL_ICH9:
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich9_gpio_registers;
size = ARRAY_SIZE(ich9_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH8M: case PCI_DEVICE_ID_INTEL_ICH8M:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich8_gpio_registers; gpio_registers = ich8_gpio_registers;

7
util/inteltool/inteltool.c
View File

@ -45,7 +45,14 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME-GMCH" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },

8
util/inteltool/inteltool.h
View File

@ -44,6 +44,12 @@
#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916
#define PCI_DEVICE_ID_INTEL_ICH9 0x2918
#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
#define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810 0x7120
@ -58,10 +64,10 @@
#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
#define PCI_DEVICE_ID_INTEL_82G33 0x29c0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0
#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
#define PCI_DEVICE_ID_INTEL_GS45 0x2a40
#define PCI_DEVICE_ID_INTEL_X58 0x3405 #define PCI_DEVICE_ID_INTEL_X58 0x3405
#define PCI_DEVICE_ID_INTEL_82443LX 0x7180 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180
/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
#define PCI_DEVICE_ID_INTEL_82443BX 0x7190 #define PCI_DEVICE_ID_INTEL_82443BX 0x7190
#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192 #define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192

4
util/inteltool/memory.c
View File

@ -54,6 +54,10 @@ int print_mchbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82830M: case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbrigde does not have MCHBAR.\n"); printf("This northbrigde does not have MCHBAR.\n");
return 1; return 1;
case PCI_DEVICE_ID_INTEL_GS45:
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
break;
default: default:
printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
return 1; return 1;

4
util/inteltool/pcie.c
View File

@ -43,6 +43,7 @@ int print_epbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break; break;
@ -95,12 +96,12 @@ int print_dmibar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
break; break;
case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810DC:
case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbrigde does not have DMIBAR.\n"); printf("This northbrigde does not have DMIBAR.\n");
return 1; return 1;
default: default:
@ -149,6 +150,7 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break; break;

117
util/inteltool/powermgt.c
View File

@ -21,47 +21,47 @@
#include <stdio.h> #include <stdio.h>
#include "inteltool.h" #include "inteltool.h"
static const io_register_t ich7_pm_registers[] = { static const io_register_t ich9_pm_registers[] = {
{ 0x00, 2, "PM1_STS" }, { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
{ 0x02, 2, "PM1_EN" }, { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
{ 0x04, 4, "PM1_CNT" }, { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
{ 0x08, 4, "PM1_TMR" }, { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
{ 0x0c, 4, "RESERVED" }, { 0x0c, 4, "RESERVED" },
{ 0x10, 4, "PROC_CNT" }, { 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK
#if DANGEROUS_REGISTERS #if DANGEROUS_REGISTERS
/* These registers return 0 on read, but reading them may cause /* These registers return 0 on read, but reading them may cause
* the system to enter C2/C3/C4 state, which might hang the system. * the system to enter Cx states, which might hang the system.
*/ */
{ 0x14, 1, "LV2 (Mobile/Ultra Mobile)" }, { 0x14, 1, "LV2 (Mobile)" },
{ 0x15, 1, "LV3 (Mobile/Ultra Mobile)" }, { 0x15, 1, "LV3 (Mobile)" },
{ 0x16, 1, "LV4 (Mobile/Ultra Mobile)" }, { 0x16, 1, "LV4 (Mobile)" },
{ 0x17, 1, "LV5 (Mobile)" },
{ 0x18, 1, "LV6 (Mobile)" },
#endif #endif
{ 0x17, 1, "RESERVED" }, { 0x19, 1, "RESERVED" },
{ 0x18, 4, "RESERVED" }, { 0x1a, 2, "RESERVED" },
{ 0x1c, 4, "RESERVED" }, { 0x1c, 4, "RESERVED" },
{ 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" }, { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
{ 0x21, 1, "RESERVED" }, { 0x2C, 4, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
{ 0x22, 2, "RESERVED" },
{ 0x24, 4, "RESERVED" },
{ 0x28, 4, "GPE0_STS" },
{ 0x2C, 4, "GPE0_EN" },
{ 0x30, 4, "SMI_EN" }, { 0x30, 4, "SMI_EN" },
{ 0x34, 4, "SMI_STS" }, { 0x34, 4, "SMI_STS" },
{ 0x38, 2, "ALT_GP_SMI_EN" }, { 0x38, 2, "ALT_GP_SMI_EN" },
{ 0x3a, 2, "ALT_GP_SMI_STS" }, { 0x3a, 2, "ALT_GP_SMI_STS" },
{ 0x3c, 4, "RESERVED" }, { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control;
{ 0x3d, 2, "RESERVED" },
{ 0x3f, 1, "RESERVED" },
{ 0x40, 2, "RESERVED" }, { 0x40, 2, "RESERVED" },
{ 0x42, 1, "GPE_CNTL" }, { 0x42, 1, "GPE_CNTL" },
{ 0x43, 1, "RESERVED" }, { 0x43, 1, "RESERVED" },
{ 0x44, 2, "DEVACT_STS" }, { 0x44, 2, "DEVACT_STS" }, // Device Activity Status
{ 0x46, 2, "RESERVED" }, { 0x46, 2, "RESERVED" },
{ 0x48, 4, "RESERVED" }, { 0x48, 4, "RESERVED" },
{ 0x4c, 4, "RESERVED" }, { 0x4c, 4, "RESERVED" },
{ 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" }, { 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK
{ 0x51, 1, "RESERVED" }, { 0x51, 1, "RESERVED" },
{ 0x52, 2, "RESERVED" }, { 0x52, 2, "RESERVED" },
{ 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" }, { 0x54, 4, "C3_RES (Mobile)" },
{ 0x58, 4, "RESERVED" }, { 0x58, 4, "C5_RES (Mobile)" },
{ 0x5c, 4, "RESERVED" }, { 0x5c, 4, "RESERVED" },
/* Here start the TCO registers */ /* Here start the TCO registers */
{ 0x60, 2, "TCO_RLD" }, { 0x60, 2, "TCO_RLD" },
@ -145,6 +145,67 @@ static const io_register_t ich8_pm_registers[] = {
{ 0x7c, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" },
}; };
static const io_register_t ich7_pm_registers[] = {
{ 0x00, 2, "PM1_STS" },
{ 0x02, 2, "PM1_EN" },
{ 0x04, 4, "PM1_CNT" },
{ 0x08, 4, "PM1_TMR" },
{ 0x0c, 4, "RESERVED" },
{ 0x10, 4, "PROC_CNT" },
#if DANGEROUS_REGISTERS
/* These registers return 0 on read, but reading them may cause
* the system to enter C2/C3/C4 state, which might hang the system.
*/
{ 0x14, 1, "LV2 (Mobile/Ultra Mobile)" },
{ 0x15, 1, "LV3 (Mobile/Ultra Mobile)" },
{ 0x16, 1, "LV4 (Mobile/Ultra Mobile)" },
#endif
{ 0x17, 1, "RESERVED" },
{ 0x18, 4, "RESERVED" },
{ 0x1c, 4, "RESERVED" },
{ 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" },
{ 0x21, 1, "RESERVED" },
{ 0x22, 2, "RESERVED" },
{ 0x24, 4, "RESERVED" },
{ 0x28, 4, "GPE0_STS" },
{ 0x2C, 4, "GPE0_EN" },
{ 0x30, 4, "SMI_EN" },
{ 0x34, 4, "SMI_STS" },
{ 0x38, 2, "ALT_GP_SMI_EN" },
{ 0x3a, 2, "ALT_GP_SMI_STS" },
{ 0x3c, 4, "RESERVED" },
{ 0x40, 2, "RESERVED" },
{ 0x42, 1, "GPE_CNTL" },
{ 0x43, 1, "RESERVED" },
{ 0x44, 2, "DEVACT_STS" },
{ 0x46, 2, "RESERVED" },
{ 0x48, 4, "RESERVED" },
{ 0x4c, 4, "RESERVED" },
{ 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
{ 0x51, 1, "RESERVED" },
{ 0x52, 2, "RESERVED" },
{ 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" },
{ 0x58, 4, "RESERVED" },
{ 0x5c, 4, "RESERVED" },
/* Here start the TCO registers */
{ 0x60, 2, "TCO_RLD" },
{ 0x62, 1, "TCO_DAT_IN" },
{ 0x63, 1, "TCO_DAT_OUT" },
{ 0x64, 2, "TCO1_STS" },
{ 0x66, 2, "TCO2_STS" },
{ 0x68, 2, "TCO1_CNT" },
{ 0x6a, 2, "TCO2_CNT" },
{ 0x6c, 2, "TCO_MESSAGE" },
{ 0x6e, 1, "TCO_WDCNT" },
{ 0x6f, 1, "RESERVED" },
{ 0x70, 1, "SW_IRQ_GEN" },
{ 0x71, 1, "RESERVED" },
{ 0x72, 2, "TCO_TMR" },
{ 0x74, 4, "RESERVED" },
{ 0x78, 4, "RESERVED" },
{ 0x7c, 4, "RESERVED" },
};
/* /*
* INTEL I/O Controller Hub 6 Family * INTEL I/O Controller Hub 6 Family
* http://www.intel.com/assets/pdf/datasheet/301473.pdf * http://www.intel.com/assets/pdf/datasheet/301473.pdf
@ -357,6 +418,16 @@ int print_pmbase(struct pci_dev *sb)
pm_registers = ich7_pm_registers; pm_registers = ich7_pm_registers;
size = ARRAY_SIZE(ich7_pm_registers); size = ARRAY_SIZE(ich7_pm_registers);
break; break;
case PCI_DEVICE_ID_INTEL_ICH9DH:
case PCI_DEVICE_ID_INTEL_ICH9DO:
case PCI_DEVICE_ID_INTEL_ICH9R:
case PCI_DEVICE_ID_INTEL_ICH9:
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich9_pm_registers;
size = ARRAY_SIZE(ich9_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH8M: case PCI_DEVICE_ID_INTEL_ICH8M:
pmbase = pci_read_word(sb, 0x40) & 0xfffc; pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich8_pm_registers; pm_registers = ich8_pm_registers;

6
util/inteltool/rootcmplx.c
View File

@ -36,6 +36,12 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH: case PCI_DEVICE_ID_INTEL_ICH7MDH:
case PCI_DEVICE_ID_INTEL_ICH9DH:
case PCI_DEVICE_ID_INTEL_ICH9DO:
case PCI_DEVICE_ID_INTEL_ICH9R:
case PCI_DEVICE_ID_INTEL_ICH9:
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
case PCI_DEVICE_ID_INTEL_ICH8M: case PCI_DEVICE_ID_INTEL_ICH8M:
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
break; break;