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rush: use generic spin table support 

With the generic spin table support in place, use that.

BUG=chrome-os-partner:32082
BRANCH=None
TEST=None

Change-Id: I7c9ebd16cd7d5e938e686df2225c612581382983
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb0d79f89e27fcd51cc751a94008b3801f5c6d0b
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Change-Id: Ic9949144ed1e9a952290d50b6726bf5891547896
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218657
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9087
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2014-09-17 11:50:46 -05:00 committed by Patrick Georgi
parent 9a9273f0c7
commit da1a0778ab
2 changed files with 3 additions and 1 deletions
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2
src/mainboard/google/rush/Kconfig
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@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_BOOTBLOCK_INIT select MAINBOARD_HAS_BOOTBLOCK_INIT
select VIRTUAL_DEV_SWITCH select VIRTUAL_DEV_SWITCH
select BOARD_ROMSIZE_KB_4096 select BOARD_ROMSIZE_KB_4096
select ARCH_SPINTABLE
config MAINBOARD_DIR config MAINBOARD_DIR
string string

2
src/mainboard/google/rush/devicetree.cb
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@ -18,6 +18,8 @@
## ##
chip soc/nvidia/tegra132 chip soc/nvidia/tegra132
register "spintable_addr" = "0x80000008"
device cpu_cluster 0 on device cpu_cluster 0 on
device cpu 0 on end device cpu 0 on end
device cpu 1 on end device cpu 1 on end