mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC

BIC uses LPCflash utility to flash FW, it uses LPC to send the
bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used
to send BIC image for in-band update support.

TEST=Use LPCflash utility to flash BIC FW on YV3 successfully.

[root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin
Update Bridge IC Firmware from LPC

Deltalake linux utility ver:1.01
build time: Feb 11 2020 14:30:55
Processing image file: Y3BRDL_D06.bin
.. of size 206968 (0x00032878) bytes
.. file will be padded to a 64-byte size
.. with DEBUG Enabled
Generating CRC-32 for file.
Done (0x4e3905a3).

iBytesRead (0x00007c00).

Discovering LPC boot loader.
Discovered @ 0x3f8.

Configuring LPC boot loader.
Configured @ 0x00000600.

Sending header block.
Sent.

Loading firmware into target.
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 16512 bytes .................
Load complete.

Update done!

Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

src/mainboard/ocp/deltalake/devicetree.cb

@@ -36,6 +36,7 @@ chip soc/intel/xeon_sp/cpx
 	register "coherency_support" = "0"
 	register "ats_support" = "0"
 
+	register "gen1_dec" = "0x00fc0601" # BIC in-band update support
 	register "gen2_dec" = "0x000c0ca1" # IPMI KCS
 
 	device cpu_cluster 0 on