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Mptable related fixes for ASUS P2B-DS. 

- Add "select IOAPIC" in the board's Kconfig file.

 - Set CONFIG_MAX_PHYSICAL_CPUS to 2 on the board. There are two
   CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
   didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).

 - Drop useless/duplicated enable_lapic() call from ASUS P2B-DS's romstage.c,
   that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
   are set.

 - Rework ASUS P2B-DS mptable.c to fix a number of things:

   - Convert it to use mptable_write_buses() as all mptable.c files should do.

   - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).

   - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-10-30 21:27:13 +00:00
parent dca8b1b599
commit da22d2190d
4 changed files with 24 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/asus/p2b-ds/Kconfig
View File

@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP
select IOAPIC
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
select SDRAMPWR_4DIMM
@ -48,4 +49,8 @@ config MAX_CPUS
int
default 2
config MAX_PHYSICAL_CPUS
int
default 2
endif # BOARD_ASUS_P2B_DS

10
src/mainboard/asus/p2b-ds/devicetree.cb
View File

@ -1,10 +1,10 @@
chip northbridge/intel/i440bx # Northbridge
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device lapic 0 on end # APIC
device lapic_cluster 0 on # (L)APIC cluster
chip cpu/intel/slot_1 # CPU socket 0
device lapic 0 on end # Local APIC of CPU 0
end
chip cpu/intel/slot_1 # CPU
device lapic 1 on end # APIC
chip cpu/intel/slot_1 # CPU socket 1
device lapic 1 on end # Local APIC of CPU 1
end
end
device pci_domain 0 on # PCI domain

64
src/mainboard/asus/p2b-ds/mptable.c
View File

@ -27,6 +27,7 @@
static void *smp_write_config_table(void *v)
{
int ioapic_id, ioapic_ver, isa_bus;
struct mp_config_table *mc;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -35,61 +36,24 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
/* Bus: Bus ID Type */
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "ISA ");
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
smp_write_ioapic(mc, 3, 0x20, res->base);
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
smp_write_ioapic(mc, 4, 0x20, res->base);
}
dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
smp_write_ioapic(mc, 5, 0x20, res->base);
}
dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
smp_write_ioapic(mc, 8, 0x20, res->base);
}
}
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
mptable_add_isa_interrupts(mc, 0x1, 0x2, 0);
/* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
0x0, 0x13, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
0x0, 0x18, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
0x0, 0x30, 0x2, 0x10);
/* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x1);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0,
MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x1, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
/* Compute the checksums. */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);

3
src/mainboard/asus/p2b-ds/romstage.c
View File

@ -25,7 +25,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb.h"
#include "northbridge/intel/i440bx/raminit.h"
@ -47,8 +46,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
enable_lapic(); /* FIXME? */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();