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nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflow 

The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide.
Clamp any values that would overflow this field. Bits in TC_DTP already
get set when the tXP and/or tXPDLL values are large.

Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-01-24 18:34:51 +01:00 committed by Patrick Georgi
parent 127455c414
commit da43737c4e
1 changed files with 4 additions and 3 deletions
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7
src/northbridge/intel/sandybridge/raminit_common.c
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@ -170,15 +170,16 @@ void dram_timing_regs(ramctr_timing *ctrl)
/* Other parameters */ /* Other parameters */
const union tc_othp_reg tc_othp = { const union tc_othp_reg tc_othp = {
.tXPDLL = ctrl->tXPDLL, .tXPDLL = MIN(ctrl->tXPDLL, 31),
.tXP = ctrl->tXP, .tXP = MIN(ctrl->tXP, 7),
.tAONPD = ctrl->tAONPD, .tAONPD = ctrl->tAONPD,
.tCPDED = 2, .tCPDED = 2,
.tPRPDEN = 1, .tPRPDEN = 1,
}; };
/* /*
* If tXP and tXPDLL are very high, we need to increase them by one. * If tXP and tXPDLL are very high, they no longer fit in the bitfields
* of the TC_OTHP register. If so, we set bits in TC_DTP to compensate.
* This can only happen on Ivy Bridge, and when overclocking the RAM. * This can only happen on Ivy Bridge, and when overclocking the RAM.
*/ */
const union tc_dtp_reg tc_dtp = { const union tc_dtp_reg tc_dtp = {