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nb/intel/pineview: Select 1M TSEG 

With the only valid GTT setting being 1M, TSEG_BASE can only be
aligned to TSEG_SIZE if it is also 1M. This alignment requirement
comes from the desire to use SMRR to protect the SMM RAM.

Tested on Foxconn D41S.

Change-Id: Ibd879529923a1676f2e78500797a52d8a37b8eef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Arthur Heymans 2019-01-12 01:38:02 +01:00 committed by Patrick Georgi
parent 786a1fec27
commit da44e34743
1 changed files with 4 additions and 4 deletions
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8
src/northbridge/intel/pineview/raminit.c
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@ -2032,9 +2032,9 @@ static void sdram_mmap_regs(struct sysinfo *s)
gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];
tom = s->channel_capacity[0];
/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
which requires to have TSEG_BASE aligned to TSEG_SIZE. */
tsegsize = 0x2;
/* with GTT always being 1M, TSEG 1M is the only setting that can
be covered by SMRR which has alignment requirements. */
tsegsize = 0x1;
mmiosize = 0x400; // 1GB
reclaim = false;
@ -2071,7 +2071,7 @@ static void sdram_mmap_regs(struct sysinfo *s)
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
reg8 &= ~0x7;
reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
reg8 |= (0 << 1) | (1 << 0); /* 1M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);
printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",