soc/intel/tigerlake: Add enum for `DdiPortXConfig`

Add an enum for `DdiPortXConfig` devicetree options. Note that setting
these options to zero does not disable the corresponding DDI port, but
instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is
connected to it.

Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>

src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb

@@ -23,11 +23,11 @@ chip soc/intel/tigerlake
 		device ref igpu on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 			# eDP
-			register "DdiPortAConfig" = "1"
+			register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 			register "DdiPortAHpd" = "1"
 			register "DdiPortADdc" = "0"
 			# HDMI
-			register "DdiPortBConfig" = "0"
+			register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
 			register "DdiPortBHpd" = "1"
 			register "DdiPortBDdc" = "1"
 		end

src/mainboard/google/deltaur/variants/baseboard/devicetree.cb

@@ -116,7 +116,7 @@ chip soc/intel/tigerlake
 	register "TcssXhciEn" = "1"
 
 	# DisplayPort
-	register "DdiPortAConfig" = "1"	# eDP
+	register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 	register "DdiPortAHpd" = "1"
 
 	# Disable PM to allow for shorter irq pulses

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -239,8 +239,8 @@ chip soc/intel/tigerlake
 	register "TcssAuxOri" = "0"
 
 	# DP port
-	register "DdiPortAConfig" = "1"	# eDP
+	register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
-	register "DdiPortBConfig" = "0"
+	register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
 
 	register "DdiPortAHpd" = "1"
 	register "DdiPortBHpd" = "1"

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -68,7 +68,7 @@ chip soc/intel/tigerlake
 	register "SataPortsEnable[1]" = "1"
 
 	# enabling EDP in PortA
-	register "DdiPortAConfig" = "1"
+	register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 
 	register "DdiPortBHpd" = "1"
 	register "DdiPort1Hpd" = "1"

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -65,7 +65,7 @@ chip soc/intel/tigerlake
 	register "PcieClkSrcUsage[3]" = "0x8"
 
 	# enabling EDP in PortA
-	register "DdiPortAConfig" = "1"
+	register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 
 	register "DdiPortAHpd" = "1"
 	register "DdiPortADdc" = "0"

src/mainboard/system76/darp7/devicetree.cb

@@ -94,12 +94,12 @@ chip soc/intel/tigerlake
 		device ref system_agent on end
 		device ref igpu on
 			# DDIA is eDP
-			register "DdiPortAConfig" = "1"
+			register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 			register "DdiPortAHpd" = "1"
 			register "DdiPortADdc" = "0"
 
 			# DDIB is HDMI
-			register "DdiPortBConfig" = "0"
+			register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
 			register "DdiPortBHpd" = "1"
 			register "DdiPortBDdc" = "1"
 

src/mainboard/system76/galp5/devicetree.cb

@@ -94,12 +94,12 @@ chip soc/intel/tigerlake
 		device ref system_agent on end
 		device ref igpu on
 			# DDIA is eDP
-			register "DdiPortAConfig" = "1"
+			register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 			register "DdiPortAHpd" = "1"
 			register "DdiPortADdc" = "0"
 
 			# DDIB is HDMI
-			register "DdiPortBConfig" = "0"
+			register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
 			register "DdiPortBHpd" = "1"
 			register "DdiPortBDdc" = "1"
 

src/mainboard/system76/gaze16/devicetree.cb

@@ -87,12 +87,12 @@ chip soc/intel/tigerlake
 		device ref system_agent on end
 		device ref igpu on
 			# DDIA is eDP
-			register "DdiPortAConfig" = "1"
+			register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 			register "DdiPortAHpd" = "1"
 			register "DdiPortADdc" = "0"
 
 			# DDIB is HDMI
-			register "DdiPortBConfig" = "0"
+			register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
 			register "DdiPortBHpd" = "1"
 			register "DdiPortBDdc" = "1"
 		end

src/mainboard/system76/lemp10/devicetree.cb

@@ -94,12 +94,12 @@ chip soc/intel/tigerlake
 		device ref system_agent on end
 		device ref igpu on
 			# DDIA is eDP
-			register "DdiPortAConfig" = "1"
+			register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 			register "DdiPortAHpd" = "1"
 			register "DdiPortADdc" = "0"
 
 			# DDIB is HDMI
-			register "DdiPortBConfig" = "0"
+			register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
 			register "DdiPortBHpd" = "1"
 			register "DdiPortBDdc" = "1"
 

src/mainboard/system76/oryp8/devicetree.cb

@@ -105,7 +105,7 @@ chip soc/intel/tigerlake
 		end
 		device ref igpu on
 			# DDIA is eDP
-			register "DdiPortAConfig" = "1"
+			register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 			register "DdiPortAHpd" = "1"
 			register "DdiPortADdc" = "0"
 		end

src/soc/intel/tigerlake/chip.h

@@ -92,6 +92,12 @@ enum slew_rate {
 	SLEW_FAST_16
 };
 
+enum ddi_port_config {
+	DDI_PORT_CFG_NO_LFP	= 0,
+	DDI_PORT_CFG_EDP	= 1,
+	DDI_PORT_CFG_MIPI_DSI	= 2,
+};
+
 struct soc_intel_tigerlake_config {
 
 	/* Common struct containing soc config data required by common code */
@@ -367,13 +373,9 @@ struct soc_intel_tigerlake_config {
 	 */
 	uint8_t gpio_pm[TOTAL_GPIO_COMM];
 
-	/* DP config */
+	/* DDI port config */
-	/*
+	enum ddi_port_config DdiPortAConfig;
-	 * Port config
+	enum ddi_port_config DdiPortBConfig;
-	 * 0:Disabled, 1:eDP, 2:MIPI DSI
-	 */
-	uint8_t DdiPortAConfig;
-	uint8_t DdiPortBConfig;
 
 	/* Enable(1)/Disable(0) HPD */
 	uint8_t DdiPortAHpd;