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soc/intel/cmn/cse: Create API to get CSE Lite WP Information 

This patch creates an API for CSE-Lite specific SKU to retrieve the
Write Protect (WP) information (`cse_log_ro_write_protection_info`)
like WP range and limit, if the region is write-protected or not etc.

BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-11-24 15:42:35 +05:30
parent 11433c8e98
commit da527ec12b
2 changed files with 26 additions and 0 deletions
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23
src/soc/intel/common/block/cse/cse_lite.c
View File

@ -10,6 +10,7 @@
#include <intelbasecode/debug_feature.h> #include <intelbasecode/debug_feature.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/cse_layout.h> #include <intelblocks/cse_layout.h>
#include <intelblocks/spi.h>
#include <security/vboot/misc.h> #include <security/vboot/misc.h>
#include <security/vboot/vboot_common.h> #include <security/vboot/vboot_common.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
@ -133,6 +134,28 @@ struct get_bp_info_rsp {
static const char * const cse_regions[] = {"RO", "RW"}; static const char * const cse_regions[] = {"RO", "RW"};
void cse_log_ro_write_protection_info(bool mfg_mode)
{
bool cse_ro_wp_en = is_spi_wp_cse_ro_en();
printk(BIOS_DEBUG, "ME: WP for RO is enabled : %s\n",
cse_ro_wp_en ? "YES" : "NO");
if (cse_ro_wp_en) {
uint32_t base, limit;
spi_get_wp_cse_ro_range(&base, &limit);
printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n",
base, limit);
}
/*
* If manufacturing mode is disabled, but CSE RO is not write protected,
* log error.
*/
if (!mfg_mode && !cse_ro_wp_en)
printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n");
}
bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp)
{ {
struct cse_boot_perf_req { struct cse_boot_perf_req {

3
src/soc/intel/common/block/include/intelblocks/cse.h
View File

@ -555,4 +555,7 @@ void soc_disable_heci1_using_pcr(void);
*/ */
void cse_get_telemetry_data(void); void cse_get_telemetry_data(void);
/* Function to log the cse WP information like range, if WP etc. */
void cse_log_ro_write_protection_info(bool mfg_mode);
#endif // SOC_INTEL_COMMON_CSE_H #endif // SOC_INTEL_COMMON_CSE_H