mb/intel/coffeelake_rvp: Add support for new coffee lake RVP8
- Add new mainboard variant coffee lake RVP8, which is CRB for
coffee lake-s processor, support U-DIMM DDR4 memory module.
- Modify cfl_h devicetree to enable IO devices, configure PCIE root
port clock source, usb over current pin as per board schematics.
- Select cannonlake PCH-H chipset config for both cfl_h & cfl_s.
- Add GPIO table as per board schematics.
BUG= None
TEST= Build and flash, confirm boot into yocoto & windows OS on both
cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA,
display, power functionalities.
Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29066
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
praveen hodagatta pranesh
Patrick Georgi
parent
92433c2878
commit
da5491a626
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@ -1,4 +1,4 @@
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if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP
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if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
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select DRIVERS_I2C_GENERIC
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select SOC_INTEL_COFFEELAKE
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select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
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select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8
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config MAINBOARD_DIR
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string
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@ -23,6 +24,7 @@ config VARIANT_DIR
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default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU
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default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11
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default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP
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default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8
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config MAINBOARD_PART_NUMBER
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string
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@ -38,6 +40,7 @@ config MAINBOARD_FAMILY
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config MAX_CPUS
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int
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default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8
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default 8
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config DEVICETREE
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@ -6,3 +6,5 @@ config BOARD_INTEL_COFFEELAKE_RVP11
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bool "-> Coffeelake H SO-DIMM DDR4 RVP11"
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config BOARD_INTEL_WHISKEYLAKE_RVP
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bool "-> Whiskeylake U DDR4 RVP"
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config BOARD_INTEL_COFFEELAKE_RVP8
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bool "-> Coffeelake S U-DIMM DDR4 RVP8"
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@ -17,6 +17,7 @@
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#if !IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
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static const struct pad_config gpio_table[] = {
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/* GPPC */
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/* A0 : RCINB_TIME_SYNC_1 */
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@ -285,6 +286,310 @@ static const struct pad_config gpio_table[] = {
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/* GPD_11 : LANPHYPC */
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};
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#else
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static const struct pad_config gpio_table[] = {
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/* GPPC */
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/* A0 : RCIN_ESPI_ALERT1 */
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/* A1 : ESPI_IO_0 */
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/* A2 : ESPI_IO_1 */
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/* A3 : ESPI_IO_2 */
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/* A4 : ESPI_IO_3 */
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/* A5 : ESPI_CSB */
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/* A6 : SERIRQ */
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/* A7 : PRIQAB_ESPI_ALERT0 */
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/* A8 : CLKRUNB */
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PAD_CFG_GPO(GPP_A8, 1, PLTRST),
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/* A9 : CLKOUT_LPC_0_ESPI_CLK */
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/* A10 : CLKOUT_LPC_1 */
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/* A11 : I2S_CODEC_INT */
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PAD_CFG_GPI_APIC_LOW(GPP_A11, UP_20K, PLTRST),
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/* A12 : BM_BUSYB_ISH__GP_6 */
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/* A13 : SUSWARNB_SUSPWRDNACK */
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PAD_CFG_GPO(GPP_A13, 1, PLTRST),
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/* A14 : SUS_STATB_ESPI_RESETB */
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/* A15 : SUSACKB */
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PAD_CFG_GPO(GPP_A15, 1, PLTRST),
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/* A16 : TCH_PAD_INT_N */
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PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, INVERT),
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/* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */
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/* A18 : ISH_GP_0 */
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/* A19 : ISH_GP_1 */
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/* A20 : ISH_GP_2 */
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/* A21 : ISH_GP_3 */
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/* A22 : ISH_GP_4 */
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/* A23 : ISH_GP_5 */
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/* B0 : SPI_TPM_INIT */
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PAD_CFG_GPI_SCI_LOW(GPP_B0, UP_20K, DEEP, EDGE_SINGLE),
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/* B1 : GSPI1_CS1 */
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/* B2 : VRALERTB */
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PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE),
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/* B3 : BT_RF_KILL */
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PAD_CFG_GPO(GPP_B3, 1, DEEP),
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/* B4 : WIFI_RF_KILL */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* B5 : SRCCLKREQB_0 */
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/* B6 : SRCCLKREQB_1 */
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/* B7 : SRCCLKREQB_2 */
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/* B8 : SRCCLKREQB_3 */
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/* B9 : SRCCLKREQB_4 */
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/* B10 : SRCCLKREQB_5 */
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/* B11 : I2S_MCLK */
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/* B12 : SLP_S0B */
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/* B13 : PLTRSTB */
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/* B14 : SPKR */
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PAD_CFG_GPO(GPP_B14, 1, PLTRST),
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/* B15 : GSPI0_CS0B */
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PAD_CFG_GPO(GPP_B15, 0, DEEP),
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/* B16 : GSPI0_CLK */
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PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),
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/* B17 : GSPI0_MISO */
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PAD_CFG_GPO(GPP_B17, 1, PLTRST),
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/* B18 : I2C_TCH_PNL_PWREN */
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PAD_CFG_GPO(GPP_B18, 1, PLTRST),
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/* B19 : GSPI1_CS0B */
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/* B20 : GSPI1_CLK */
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/* B21 : GSPI1_MISO */
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/* B22 : GSP1_MOSI */
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/* B23 : EC_SLP_S0_CS_N */
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PAD_CFG_GPO(GPP_B23, 1, PLTRST),
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/* C0 : SMBCLK */
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/* C1 : SMBDATA */
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/* C2 : SMBALERTB */
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PAD_CFG_GPO(GPP_C2, 1, DEEP),
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/* C3 : SML0CLK */
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/* C4 : SML0DATA */
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/* C5 : WIFI_WAKE_N */
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PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL),
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/* C6 : SML1CLK */
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/* C7 : SML1DATA */
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/* C8 : UART0_RXD */
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PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT),
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/* C9 : UART0_TXD */
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PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE),
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/* C10 : UART0_RTSB */
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PAD_CFG_GPO(GPP_C10, 0, PLTRST),
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/* C11 : UART0_CTSB */
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PAD_CFG_TERM_GPO(GPP_C11, 1, UP_20K, DEEP),
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/* C12 : UART1_RXD_ISH_UART1_RXD */
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PAD_CFG_GPO(GPP_C12, 1, PLTRST),
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/* C13 : UART1_RXD_ISH_UART1_TXD */
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/* C14 : SSD1_RESET */
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PAD_CFG_GPO(GPP_C14, 1, PLTRST),
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/* C15 : SSD2_RESET */
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PAD_CFG_GPO(GPP_C15, 1, PLTRST),
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/* C16 : I2C0_SDA */
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/* C17 : I2C0_SCL */
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/* C18 : I2C1_SDA */
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/* C19 : I2C1_SCL */
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/* C20 : UART2_RXD */
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/* C21 : UART2_TXD */
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/* C22 : UART2_RTSB */
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/* C23 : UART2_CTSB */
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/* D0 : SPI1_CSB_BK_0 */
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/* D1 : SPI1_CLK_BK_1 */
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/* D2 : SPI1_MISO_IO_1_BK_2 */
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/* D3 : SPI1_MOSI_IO_0_BK_3 */
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/* D4 : IMGCLKOUT_0_BK_4 */
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/* D5 : ISH_I2C0_SDA */
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/* D6 : ISH_I2C0_SCL */
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/* D7 : SSP2_RXD */
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PAD_CFG_GPI_INT(GPP_D7, NONE, PLTRST, LEVEL),
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/* D8 : SSP2_SCLK */
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PAD_CFG_GPI_INT(GPP_D8, NONE, PLTRST, LEVEL),
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/* D9 : ISH_SPI_CSB */
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PAD_CFG_GPO(GPP_D9, 1, PLTRST),
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/* D10 : ISH_SPI_CLK */
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PAD_CFG_GPI_APIC(GPP_D10, UP_20K, PLTRST, LEVEL, INVERT),
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/* D11 : ISH_SPI_MISO_GP_BSSB_CLK */
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PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),
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/* D12 : ISH_SPI_MOSI_GP_BSSB_DI */
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/* D13 : ISH_UART0_RXD_SML0BDATA */
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PAD_CFG_GPO(GPP_D13, 1, DEEP),
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/* D14 : ISH_UART0_TXD_SML0BCLK */
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PAD_CFG_GPO(GPP_D14, 1, PLTRST),
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/* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */
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/* D16 : ISH_UART0_CTSB_SML0BALERTB */
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PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),
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/* D17 : DMIC_CLK_1_SNDW3_CLK */
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/* D18 : DMIC_DATA_1_SNDW3_DATA */
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/* D19 : DMIC_CLK_0_SNDW4_CLK */
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/* D20 : DMIC_DATA_0_SNDW4_DATA */
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/* D21 : SPI1_IO_2 */
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PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),
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/* D22 : SPI1_IO_3 */
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PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),
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/* D23 : ISH_I2C2_SCL_I2C3_SCL */
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/* E0 : SATAXPCIE_0_SATAGP_0 */
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/* E1 : SATAXPCIE_1_SATAGP_1 */
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/* E2 : SATAXPCIE_2_SATAGP_2 */
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PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),
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/* E3 : EC_SMI_N */
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PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),
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/* E4 : SATA_DEVSLP_0 */
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PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
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/* E5 : SATA_DEVSLP_1 */
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/* E6 : SATA_DEVSLP_2 */
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PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE),
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/* E7 : CPU_GP_1 */
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PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE),
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/* E8 : SATA_LEDB */
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/* E9 : USB2_OCB_0 */
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/* E10 : USB2_OCB_1 */
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/* E11 : USB2_OCB_2 */
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/* E12 : USB2_OCB_3 */
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/* F0 : SATAXPCIE_3_SATAGP_3 */
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/* F1 : SATAXPCIE_4_SATAGP_4 */
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/* F2 : SATAXPCIE_5_SATAGP_5 */
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/* F3 : SATAXPCIE_6_SATAGP_6 */
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/* F4 : SLOT2_RST_N */
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PAD_CFG_GPO(GPP_F4, 1, PLTRST),
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/* F5 : SATA_DEVSLP_3 */
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/* F6 : SATA_DEVSLP_4 */
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/* F7 : ME_PG_LED */
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PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, LEVEL),
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/* F8 : SATA_DEVSLP_6 */
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/* F9 : PEG_SLOT_RST */
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PAD_CFG_GPO(GPP_F9, 1, PLTRST),
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/* F10 : BIOS_RECOVERY */
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PAD_CFG_GPI_INT(GPP_F10, NONE, PLTRST, LEVEL),
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/* F11 : SATA_SLOAD */
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/* F12 : SATA_S-DATA_OUT1 */
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/* F13 : SATA_S-DATA_OUT0 */
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/* F14 : PS_ON */
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/* F15 : USB2_OC_4 */
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/* F16 : USB2_OC_5 */
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/* F17 : USB2_OC_6 */
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/* F18 : USB2_OC_7 */
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/* F19 : EDP_VDDEN */
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/* F20 : EDP_BKLTEN */
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/* F21 : EDP_BKLTCTL */
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/* F22 : DDPF_C_TRLCLK */
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/* F23 : DDPF_C_TRLDATA */
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/* G0 : SD_DATA */
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/* G1 : SD_DATA0 */
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/* G2 : SD_DATA1 */
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/* G3 : SD_DATA2 */
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/* G4 : SD_DATA3 */
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/* G5 : GPP_G_5_SD3_CDB */
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PAD_CFG_NF(GPP_G5, UP_20K, DEEP, GPIO),
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/* G6 : SD_CLK */
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/* G7 : GPP_G_7_SD3_WP */
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PAD_CFG_NF(GPP_G7, UP_20K, DEEP, GPIO),
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/* H0 : SRCCLKREQB_6 */
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/* H1 : SRCCLKREQB_7 */
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/* H2 : SRCCLKREQB_8 */
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/* H3 : SRCCLKREQB_9 */
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/* H4 : SRCCLKREQB_10 */
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/* H5 : SRCCLKREQB_11 */
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/* H6 : SRCCLKREQB_12 */
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/* H7 : SRCCLKREQB_13 */
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/* H8 : SRCCLKREQB_14 */
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/* H9 : SRCCLKREQB_15 */
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/* H10 : Audio Power Enable */
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PAD_CFG_GPO(GPP_H10, 1, PLTRST),
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/* H11 : SML_2_DATA */
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/* H12 : SML_2_ALERT */
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/* H13 : SML_3_CLK */
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/* H14 : SML_3_DATA */
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/* H15 : SML_3_ALERT */
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/* H16 : TBT_CIO_PWREN */
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PAD_CFG_GPO(GPP_H16, 1, PLTRST),
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/* H17 : TBT_FORCE_PWR */
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PAD_CFG_GPO(GPP_H17, 0, PLTRST),
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/* H18 : SML_4_ALERT */
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/* H19 : ISH_I2C0_SDA */
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/* H20 : ISH_I2C0_SCL */
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/* H21 : ISH_I2C1_SDA */
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/* H22 : ISH_I2C1_SCL */
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/* H23 : TBT_CIO_PLUG_EVENT_N */
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PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE),
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/* I0 : DDPB_HPD_0 */
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/* I1 : DDPC_HPD_1 */
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/* I2 : DPPD_HPD_2 */
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/* I3 : DPPE_HPD_3 */
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/* I4 : EDP_HPD */
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/* I5 : DDPB_C_TRLCLK */
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/* I6 : DDPB_C_TRLDATA */
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/* I7 : DDPC_C_TRLCLK */
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/* I8 : DDPC_C_TRLDATA */
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/* I9 : DDPD_C_TRLCLK */
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/* I10 : DDPD_C_TRLDATA */
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/* I11 : M2_SKT2_C_FG0 */
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/* I12 : M2_SKT2_CFG1 */
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/* I13 : M2_SKT2_C_FG2 */
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/* I14 : M2_SKT2_C_FG3 */
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/* J0 : I2C_TCH_PNL_INT */
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PAD_CFG_GPI_APIC(GPP_J0, UP_20K, PLTRST, EDGE_SINGLE, INVERT),
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/* J1 : CPU_C10_GATE */
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/* J2 : FPS_INT_N */
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PAD_CFG_GPI_APIC(GPP_J2, NONE, PLTRST, EDGE_SINGLE, NONE),
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/* J3 : FPS_RST_N */
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PAD_CFG_GPO(GPP_J3, 1, PLTRST),
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/* J4 : CNV_BRI_DT_UART0_RTS */
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/* J5 : CNV_BRI_RSP_UART0_RXD */
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/* J6 : CNV_RGI_DT_UART0_TXD */
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/* J7 : CNV_RGI_RSP_UART0_CTS */
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/* J8 : CNV_M_FUART2_RXD */
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/* J9 : CNV_M_FUART2_TXD */
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/* J10 : I2C_TCH_PNL_RST_N */
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PAD_CFG_GPO(GPP_J10, 1, PLTRST),
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/* J11 : SPEAKER_PD */
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PAD_CFG_GPO(GPP_J11, 1, PLTRST),
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/* K0 : GPP_K0 */
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/* K1 : SATA_ODD_PWRGT_R */
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PAD_CFG_GPO(GPP_K1, 1, PLTRST),
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/* K2 : SATA_ODD_DA_N */
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PAD_CFG_GPI_SCI_HIGH(GPP_K2, NONE, PLTRST, EDGE_SINGLE),
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/* K3 : GPP_K3 */
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/* K4 : GPP_K4 */
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/* K5 : GPP_K5 */
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/* K6 : GPP_K6 */
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/* K7 : GPP_K7 */
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/* K8 : GPP_K8 */
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/* K9 : GPP_K9 */
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/* K10 : GPP_K10 */
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/* K11 : RUNTIME_SCI */
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PAD_CFG_GPI_SCI_LOW(GPP_K11, UP_20K, PLTRST, LEVEL),
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/* K12 : GSXDOUT */
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/* K13 : GSXSLOAD */
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/* K14 : GSXDIN */
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/* K15 : GSXSRESET */
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/* K16 : GSXCLK */
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/* K17 : ADR_COMPLETE */
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/* K18 : SLOT2_WAKE_N */
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PAD_CFG_GPI_SCI_LOW(GPP_K18, NONE, PLTRST, LEVEL),
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/* K19 : SMI */
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/* K20 : GPP_K20 */
|
||||
/* K21 : GPP_K21 */
|
||||
/* K22 : IMGCLKOUT_0 */
|
||||
/* K23 : IMGCLKOUT_1 */
|
||||
|
||||
/* GPD */
|
||||
/* GPD_0 : BATLOWB */
|
||||
/* GPD_1 : ACPRESENT */
|
||||
/* GPD_2 : LAN_WAKEB */
|
||||
/* GPD_3 : PWRBTNB */
|
||||
/* GPD_4 : SLP_S3B */
|
||||
/* GPD_5 : SLP_S4B */
|
||||
/* GPD_6 : SLP_AB */
|
||||
/* GPD_7 : GPD_7 */
|
||||
/* GPD-8 : SUSCLK */
|
||||
/* GPD-9 : SLP_WLANB */
|
||||
/* GPD-10 : SLP_5B */
|
||||
/* GPD_11 : LANPHYPC */
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
|
||||
|
|
|
|||
|
|
@ -6,31 +6,48 @@ chip soc/intel/cannonlake
|
|||
|
||||
# FSP configuration
|
||||
register "SaGv" = "3"
|
||||
register "RMT" = "1"
|
||||
register "SmbusEnable" = "1"
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC6)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC2)"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC7)"
|
||||
register "usb2_ports[10]" = "USB2_PORT_MID(OC7)"
|
||||
register "usb2_ports[11]" = "USB2_PORT_MID(OC3)"
|
||||
register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"
|
||||
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC7)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)"
|
||||
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC7)"
|
||||
|
||||
register "PchHdaDspEnable" = "1"
|
||||
register "SataSalpSupport" = "1"
|
||||
register "SataPortsEnable[0]" = "1"
|
||||
register "SataPortsEnable[1]" = "1"
|
||||
register "SataPortsEnable[2]" = "1"
|
||||
register "SataPortsEnable[3]" = "1"
|
||||
register "SataPortsEnable[4]" = "1"
|
||||
register "SataPortsEnable[5]" = "1"
|
||||
register "SataPortsEnable[6]" = "1"
|
||||
register "SataPortsEnable[7]" = "1"
|
||||
|
||||
register "PchHdaDspEnable" = "0"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
register "PchHdaAudioLinkSsp0" = "1"
|
||||
register "PchHdaAudioLinkSsp1" = "1"
|
||||
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpEnable[1]" = "1"
|
||||
|
|
@ -46,13 +63,25 @@ chip soc/intel/cannonlake
|
|||
register "PcieRpEnable[11]" = "1"
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieRpEnable[13]" = "1"
|
||||
register "PcieRpEnable[14]" = "1"
|
||||
register "PcieRpEnable[15]" = "1"
|
||||
register "PcieRpEnable[16]" = "1"
|
||||
register "PcieRpEnable[17]" = "1"
|
||||
register "PcieRpEnable[18]" = "1"
|
||||
register "PcieRpEnable[19]" = "1"
|
||||
register "PcieRpEnable[20]" = "1"
|
||||
register "PcieRpEnable[21]" = "1"
|
||||
register "PcieRpEnable[22]" = "1"
|
||||
register "PcieRpEnable[23]" = "1"
|
||||
|
||||
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[0]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "8"
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
|
||||
register "PcieClkSrcUsage[3]" = "14"
|
||||
register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[5]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[3]" = "0x6"
|
||||
register "PcieClkSrcUsage[4]" = "0x18"
|
||||
register "PcieClkSrcUsage[5]" = "14"
|
||||
register "PcieClkSrcUsage[8]" = "0x40"
|
||||
register "PcieClkSrcUsage[9]" = "PCIE_CLK_LAN"
|
||||
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
|
|
@ -60,15 +89,14 @@ chip soc/intel/cannonlake
|
|||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
register "PcieClkSrcClkReq[8]" = "8"
|
||||
register "PcieClkSrcClkReq[9]" = "9"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "GPP_G5"
|
||||
|
||||
# Enable S0ix
|
||||
register "s0ix_enable" = "1"
|
||||
# HECI
|
||||
register "HeciEnabled" = "1"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
|
|
@ -79,29 +107,19 @@ chip soc/intel/cannonlake
|
|||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
device pci 14.5 on end # SDCard
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ALPS0001""
|
||||
register "generic.desc" = ""Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
|
||||
register "hid_desc_reg_offset" = "0x1"
|
||||
device i2c 2C on end
|
||||
end
|
||||
end # I2C 0
|
||||
device pci 15.0 on end # I2C #0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 on end # I2C #3
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 off end # SATA
|
||||
device pci 19.0 on end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 off end # I2C #4
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
|
||||
|
|
@ -128,9 +146,9 @@ chip soc/intel/cannonlake
|
|||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 off end # Intel HDA
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
device pci 1f.6 on end # GbE
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -0,0 +1,161 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "3"
|
||||
register "RMT" = "1"
|
||||
register "SmbusEnable" = "1"
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC5)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC5)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"
|
||||
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"
|
||||
register "usb2_ports[10]" = "USB2_PORT_MID(OC3)"
|
||||
register "usb2_ports[11]" = "USB2_PORT_MID(OC6)"
|
||||
register "usb2_ports[12]" = "USB2_PORT_MID(OC6)"
|
||||
register "usb2_ports[13]" = "USB2_PORT_EMPTY"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)"
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC3)"
|
||||
|
||||
register "SataSalpSupport" = "1"
|
||||
register "SataPortsEnable[0]" = "1"
|
||||
register "SataPortsEnable[1]" = "1"
|
||||
register "SataPortsEnable[2]" = "1"
|
||||
register "SataPortsEnable[3]" = "1"
|
||||
register "SataPortsEnable[4]" = "1"
|
||||
register "SataPortsEnable[5]" = "1"
|
||||
register "SataPortsEnable[6]" = "1"
|
||||
register "SataPortsEnable[7]" = "1"
|
||||
|
||||
register "PchHdaDspEnable" = "0"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpEnable[1]" = "1"
|
||||
register "PcieRpEnable[2]" = "1"
|
||||
register "PcieRpEnable[3]" = "1"
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpEnable[9]" = "1"
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpEnable[11]" = "1"
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieRpEnable[13]" = "1"
|
||||
register "PcieRpEnable[14]" = "1"
|
||||
register "PcieRpEnable[15]" = "1"
|
||||
register "PcieRpEnable[16]" = "1"
|
||||
register "PcieRpEnable[17]" = "1"
|
||||
register "PcieRpEnable[18]" = "1"
|
||||
register "PcieRpEnable[19]" = "1"
|
||||
register "PcieRpEnable[20]" = "1"
|
||||
register "PcieRpEnable[21]" = "1"
|
||||
register "PcieRpEnable[22]" = "1"
|
||||
register "PcieRpEnable[23]" = "1"
|
||||
|
||||
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[1]" = "8"
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
|
||||
register "PcieClkSrcUsage[3]" = "0x6"
|
||||
register "PcieClkSrcUsage[4]" = "0x18"
|
||||
register "PcieClkSrcUsage[5]" = "1"
|
||||
register "PcieClkSrcUsage[6]" = "0x8"
|
||||
register "PcieClkSrcUsage[8]" = "0x40"
|
||||
register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[10]" = "0x14"
|
||||
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
register "PcieClkSrcClkReq[6]" = "6"
|
||||
register "PcieClkSrcClkReq[8]" = "8"
|
||||
register "PcieClkSrcClkReq[9]" = "9"
|
||||
register "PcieClkSrcClkReq[10]" = "10"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# HECI
|
||||
register "HeciEnabled" = "1"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
device pci 14.5 on end # SDCard
|
||||
device pci 15.0 on end # I2C 0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 on end # I2C #2
|
||||
device pci 15.3 on end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 off end # I2C #4
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 off end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1b.0 on end # PCI Express Port 17
|
||||
device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 on end # GbE
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue