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southbridge/intel/lynxpoint: use common Intel ACPI hardware definitions 

Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I03051c1c1df3e64abeedd6370a440111ade59742
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15676
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-07-13 23:23:16 -05:00
parent 340898f21a
commit da5f5094f0
5 changed files with 16 additions and 20 deletions
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1
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -20,6 +20,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON
select IOAPIC
select HAVE_HARD_RESET

9
src/southbridge/intel/lynxpoint/pch.h
View File

@ -17,6 +17,8 @@
#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
#define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
#include <arch/acpi.h>
/*
* Lynx Point PCH PCI Devices:
*
@ -696,13 +698,6 @@ void pch_enable_lpc(void);
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP (7 << 10)
#define SLP_TYP_S0 0
#define SLP_TYP_S1 1
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)

20
src/southbridge/intel/lynxpoint/smihandler.c
View File

@ -124,10 +124,10 @@ static void southbridge_smi_sleep(void)
/* Figure out SLP_TYP */
reg32 = inl(pmbase + PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
slp_typ = (reg32 >> 10) & 7;
slp_typ = acpi_sleep_from_pm1(reg32);
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ-2);
mainboard_smi_sleep(slp_typ);
/* USB sleep preparations */
#if !CONFIG_FINALIZE_USB_ROUTE_XHCI
@ -138,30 +138,30 @@ static void southbridge_smi_sleep(void)
#if CONFIG_ELOG_GSMI
/* Log S3, S4, and S5 entry */
if (slp_typ >= 5)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
#endif
/* Next, do the deed.
*/
switch (slp_typ) {
case SLP_TYP_S0:
case ACPI_S0:
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
break;
case SLP_TYP_S1:
case ACPI_S1:
printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
break;
case SLP_TYP_S3:
case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */
wbinvd();
break;
case SLP_TYP_S4:
case ACPI_S4:
printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
break;
case SLP_TYP_S5:
case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */
@ -193,7 +193,7 @@ static void southbridge_smi_sleep(void)
enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
if (slp_typ >= ACPI_S3)
halt();
/* In most sleep states, the code flow of this function ends at

4
src/southbridge/intel/lynxpoint/usb_ehci.c
View File

@ -71,8 +71,8 @@ void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
pci_cmd = pci_read_config32(dev, PCI_COMMAND);
switch (slp_typ) {
case SLP_TYP_S4:
case SLP_TYP_S5:
case ACPI_S4:
case ACPI_S5:
/* Check if controller is in D3 power state */
pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS);
if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {

2
src/southbridge/intel/lynxpoint/usb_xhci.c
View File

@ -162,7 +162,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
u32 reg32;
u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || slp_typ < 3)
if (!mem_base || slp_typ < ACPI_S3)
return;
if (pch_is_lp()) {