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soc/intel/skylake: Set PsysPmax value 

According to doc #543977 Power Architecture Guide, PsysPmax is the
maximum platform power. It maps to the full-scale of Psys signal.
This patch adds a "psys_pmax" member in chip information which allows
boards to set up maximum platform power.

BUG=b:71594855
BRANCH=None
TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz
     chromeos-mrc coreboot chromeos-bootimage" & ensure correct
     PsysPmax value is passed to FSP-S through UPD. Verfied on
     KBL-R and KBL-U SKUs.

Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Gaggery Tsai 2018-01-15 15:03:01 +08:00 committed by Shelley Chen
parent c12dff9098
commit da6f4ae0b9
2 changed files with 9 additions and 1 deletions
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3
src/soc/intel/skylake/chip.h
View File

@ -110,6 +110,9 @@ struct soc_intel_skylake_config {
/* PL4 Value in Watts */
u32 tdp_pl4;
/* Estimated maximum platform power in Watts */
u16 psys_pmax;
/*
* The following fields come from FspUpdVpd.h.
* These are configuration values that are passed to FSP during

7
src/soc/intel/skylake/chip_fsp20.c
View File

@ -93,7 +93,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
static struct soc_intel_skylake_config *config;
uintptr_t vbt_data = 0;
int i;
int is_s3_wakeup = acpi_is_wakeup_s3();
@ -106,6 +105,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
config = dev->chip_info;
mainboard_silicon_init_params(params);
/* Set PsysPmax if it is available from DT */
if (config->psys_pmax) {
/* PsysPmax is in unit of 1/8 Watt */
tconfig->PsysPmax = config->psys_pmax * 8;
printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax);
}
/* Load VBT */
if (is_s3_wakeup) {