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mb/pcengines/apu1: Use fixed acpimmio_base 

Change-Id: Iaaa0cc0b486145517939f46943f2fee82053d98e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Kyösti Mälkki 2020-06-01 09:27:13 +03:00 committed by Patrick Georgi
parent 7f32df379c
commit da6fcb13f1
4 changed files with 18 additions and 37 deletions
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16
src/mainboard/pcengines/apu1/gpio_ftns.c
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@ -5,16 +5,7 @@
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include "gpio_ftns.h" #include "gpio_ftns.h"
uintptr_t find_gpio_base(void) void configure_gpio(u8 gpio, u8 iomux_ftn, u8 setting)
{
uintptr_t base_addr;
/* Get the ACPIMMIO base address */
base_addr = pm_read32(0x24);
base_addr &= 0xFFFFF000;
return base_addr;
}
void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting)
{ {
u8 bdata; u8 bdata;
@ -26,14 +17,13 @@ void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting)
gpio_100_write8(gpio, bdata); gpio_100_write8(gpio, bdata);
} }
u8 read_gpio(uintptr_t base_addr, u8 gpio) u8 read_gpio(u8 gpio)
{ {
return (gpio_100_read8(gpio) & GPIO_DATA_IN) ? 1 : 0; return (gpio_100_read8(gpio) & GPIO_DATA_IN) ? 1 : 0;
} }
int get_spd_offset(void) int get_spd_offset(void)
{ {
uintptr_t base_addr = find_gpio_base(); u8 spd_offset = read_gpio(GPIO_16);
u8 spd_offset = read_gpio(base_addr, GPIO_16);
return spd_offset; return spd_offset;
} }

7
src/mainboard/pcengines/apu1/gpio_ftns.h
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@ -5,13 +5,10 @@
#include <stdint.h> #include <stdint.h>
uintptr_t find_gpio_base(void); void configure_gpio(u8 gpio, u8 iomux_ftn, u8 setting);
void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting); u8 read_gpio(u8 gpio);
u8 read_gpio(uintptr_t base_addr, u8 gpio);
int get_spd_offset(void); int get_spd_offset(void);
#define IOMUX_OFFSET 0xD00
#define GPIO_OFFSET 0x100
#define GPIO_10 10 // PE3 Reset #define GPIO_10 10 // PE3 Reset
#define GPIO_11 11 // PE4 Reset #define GPIO_11 11 // PE4 Reset
#define GPIO_15 15 // board rev strap ms bit #define GPIO_15 15 // board rev strap ms bit

9
src/mainboard/pcengines/apu1/mainboard.c
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@ -362,8 +362,6 @@ const char *smbios_system_sku(void)
static void mainboard_final(void *chip_info) static void mainboard_final(void *chip_info)
{ {
u32 mmio_base;
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n"); printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n");
/* /*
@ -371,10 +369,9 @@ static void mainboard_final(void *chip_info)
* LED2/D6/GPIO_190 should be 1 * LED2/D6/GPIO_190 should be 1
* LED3/D5/GPIO_191 should be 1 * LED3/D5/GPIO_191 should be 1
*/ */
mmio_base = find_gpio_base(); configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
usb_oc_setup(); usb_oc_setup();
} }

23
src/mainboard/pcengines/apu1/romstage.c
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@ -8,8 +8,6 @@
static void early_lpc_init(void) static void early_lpc_init(void)
{ {
u32 mmio_base;
/* PC Engines requires system boot when power is applied. This feature is /* PC Engines requires system boot when power is applied. This feature is
* controlled in PM_REG 5Bh register. "Always Power On" works by writing a * controlled in PM_REG 5Bh register. "Always Power On" works by writing a
* value of 05h. * value of 05h.
@ -26,17 +24,16 @@ static void early_lpc_init(void)
pm_write8(SB_PMIOA_REGEA, bdata); pm_write8(SB_PMIOA_REGEA, bdata);
//configure required GPIOs //configure required GPIOs
mmio_base = find_gpio_base(); configure_gpio(GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
configure_gpio(mmio_base, GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); configure_gpio(GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
configure_gpio(mmio_base, GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); configure_gpio(GPIO_15, GPIO_FTN_1, GPIO_INPUT);
configure_gpio(mmio_base, GPIO_15, GPIO_FTN_1, GPIO_INPUT); configure_gpio(GPIO_16, GPIO_FTN_1, GPIO_INPUT);
configure_gpio(mmio_base, GPIO_16, GPIO_FTN_1, GPIO_INPUT); configure_gpio(GPIO_17, GPIO_FTN_1, GPIO_INPUT);
configure_gpio(mmio_base, GPIO_17, GPIO_FTN_1, GPIO_INPUT); configure_gpio(GPIO_18, GPIO_FTN_1, GPIO_INPUT);
configure_gpio(mmio_base, GPIO_18, GPIO_FTN_1, GPIO_INPUT); configure_gpio(GPIO_187, GPIO_FTN_1, GPIO_INPUT);
configure_gpio(mmio_base, GPIO_187, GPIO_FTN_1, GPIO_INPUT); configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
} }
void board_BeforeAgesa(struct sysinfo *cb) void board_BeforeAgesa(struct sysinfo *cb)