vendorcode/intel/fsp: Add fsp 2.0 header files for skylake and kabylake

Add FSP 2.0 header files, these files are common for Skylake
and Kabylake, name the folder as skykabylake to signify the same.

Change-Id: I71b43a59c9a9b0adf1ee48285e4a72e24a13df2d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/CpuConfigFspData.h

@@ -0,0 +1,68 @@
+/** @file
+  FSP CPU Data Config Block.
+
+@copyright
+  Copyright (c) 2016 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by the
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+  This file contains an 'Intel Peripheral Driver' and is uniquely
+  identified as "Intel Reference Module" and is licensed for Intel
+  CPUs and chipsets under the terms of your license agreement with
+  Intel or your vendor. This file may be modified by the user, subject
+  to additional terms of the license agreement.
+
+@par Specification Reference:
+**/
+#ifndef _CPU_CONFIG_FSP_DATA_H_
+#define _CPU_CONFIG_FSP_DATA_H_
+union CPU_CONFIG_FSP_DATA {
+  struct {
+    /**
+      Enable or Disable Advanced Encryption Standard (AES) feature.
+      For some countries, this should be disabled for legal reasons.
+      -    0: Disable
+      - <b>1: Enable</b>
+    **/
+    uint32_t AesEnable           : 1;
+    /**
+    Processor Early Power On Configuration FCLK setting.
+     - <b>0: 800 MHz (ULT/ULX)</b>.
+     - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
+     - 2: 400 MHz.
+     - 3: Reserved.
+    **/
+    uint32_t FClkFrequency       : 2;
+    uint32_t EnableRsr           : 1;                 ///< Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
+    /**
+    Policies to obtain CPU temperature.
+     - <b>0: ACPI thermal management uses EC reported temperature values</b>.
+     - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.
+     - 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition.
+    **/
+    uint32_t EnableDts           : 2;
+    uint32_t SmmbaseSwSmiNumber  : 8;                 ///< Software SMI number for handler to save CPU information in SMRAM.
+    /**
+      Enable or Disable Virtual Machine Extensions (VMX) feature.
+      -    0: Disable
+      - <b>1: Enable</b>
+    **/
+    uint32_t VmxEnable           : 1;
+    /**
+      Enable or Disable Trusted Execution Technology (TXT) feature.
+      -    0: Disable
+      - <b>1: Enable</b>
+    **/
+    uint32_t TxtEnable           : 1;
+    uint32_t SkipMpInit          : 1;                 ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
+    uint32_t RsvdBits            : 15;                ///< Reserved for future use
+    uint64_t MicrocodePatchAddress;     ///< Pointer to microcode patch that is suitable for this processor.
+  } Bits;
+  uint32_t Uint32[3];
+};
+
+#endif // _CPU_CONFIG_FSP_DATA_H_

src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspUpd.h

@@ -0,0 +1,42 @@
+/** @file
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#define FSPT_UPD_SIGNATURE               0x545F4450554C424B        /* 'KBLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE               0x4D5F4450554C424B        /* 'KBLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE               0x535F4450554C424B        /* 'KBLUPD_S' */
+
+#endif