Fixes to enable RC6 on IvyBridge
- The unneeded poll on non-MT force-wake bit was timing out and causing the gma_pm_init_pre_vbios() function to exit early so it was not preparing PM registers properly. I changed the gtt_poll() calls to not return on timeout unless it can't proceed so we don't see half-initialized registers. - RC6+ (Deep Render Standby) is not working reliably so we can just enable RC6 in the BIOS and let the kernel decide if it wants to enable RC6+ later. This Kernel message is new in kernel 3.4: [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1268 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -374,19 +374,11 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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if (bridge_silicon_revision() < IVB_STEP_C0) {
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/* 1: Enable force wake */
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gtt_write(0xa18c, 0x00000001);
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if (!gtt_poll(0x130090, (1 << 0), (1 << 0)))
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return;
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gtt_poll(0x130090, (1 << 0), (1 << 0));
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} else {
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gtt_write(0xa180, 1 << 5);
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gtt_write(0xa188, 0xffff0001);
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if (!gtt_poll(0x130040, (1 << 0), (1 << 0)))
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return;
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/*
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* HACK: also poll on 0x130090, for some reason graphics does
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* not work on all SKUs unless this register is polled at boot.
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*/
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if (!gtt_poll(0x130090, (1 << 0), (1 << 0)))
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return;
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gtt_poll(0x130040, (1 << 0), (1 << 0));
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}
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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@ -432,7 +424,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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gtt_write_powermeter(ivb_pm_gt2_17w);
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} else if ((tdp >= 25) && (tdp <= 35)) {
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/* 25W-35W */
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printk(BIOS_DEBUG, "IVB GT2 35W "
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printk(BIOS_DEBUG, "IVB GT2 25W-35W "
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"Power Meter Weights\n");
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gtt_write_powermeter(ivb_pm_gt2_35w);
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} else {
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@ -472,8 +464,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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reg32 &= 0xf;
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reg32 |= (1 << 1);
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gtt_write(0x941c, reg32);
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if (!gtt_poll(0x941c, (1 << 1), (0 << 1)))
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return;
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gtt_poll(0x941c, (1 << 1), (0 << 1));
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}
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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@ -489,15 +480,13 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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}
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/* 7 */
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if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
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return;
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gtt_write(0x138128, 0x00000029); /* Mailbox Data */
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gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
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if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
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return;
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gtt_write(0x138124, 0x8000000a); /* Mailbox Cmd to clear RC6 count */
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if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
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return;
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if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
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gtt_write(0x138128, 0x00000029); /* Mailbox Data */
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gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
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if (gtt_poll(0x138124, (1 << 31), (0 << 31)))
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gtt_write(0x138124, 0x8000000a);
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gtt_poll(0x138124, (1 << 31), (0 << 31));
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}
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/* 8 */
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gtt_write(0xa090, 0x00000000); /* RC Control */
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@ -530,8 +519,13 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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/* 11a: Enable Render Standby (RC6) */
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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/* on IVB: also enable DeepRenderStandby */
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gtt_write(0xa090, 0x88060000); /* HW RC Control */
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/*
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* IvyBridge should also support DeepRenderStandby.
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*
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* Unfortunately it does not work reliably on all SKUs so
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* disable it here and it can be enabled by the kernel.
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*/
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gtt_write(0xa090, 0x88040000); /* HW RC Control */
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} else {
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gtt_write(0xa090, 0x88040000); /* HW RC Control */
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}
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@ -566,22 +560,11 @@ static void gma_pm_init_post_vbios(struct device *dev)
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/* 15: Deassert Force Wake */
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if (bridge_silicon_revision() < IVB_STEP_C0) {
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gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
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if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) {
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return;
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}
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gtt_poll(0x130090, (1 << 0), (0 << 0));
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} else {
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gtt_write(0xa188, 0x1fffe);
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if (!gtt_poll(0x130040, (1 << 0), (0 << 0))) {
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return;
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}
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/*
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* HACK: also poll on 0x130090, for some reason graphics does
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* not work on all SKUs unless this register is polled at boot.
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*/
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if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) {
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return;
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}
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gtt_write(0xa188, gtt_read(0xa188) | 1);
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if (gtt_poll(0x130040, (1 << 0), (0 << 0)))
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gtt_write(0xa188, gtt_read(0xa188) | 1);
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}
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/* 16: SW RC Control */
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