nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -17,6 +17,7 @@
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <superio/nuvoton/nct6776/nct6776.h>
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#include <superio/nuvoton/nct6776/nct6776.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/common/nuvoton.h>
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@ -18,6 +18,7 @@
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <superio/smsc/sio1007/chip.h>
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#include <superio/smsc/sio1007/chip.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#define SIO_PORT 0x164e
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#define SIO_PORT 0x164e
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@ -25,6 +25,7 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/common/gpio.h>
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#include "ec/google/chromeec/ec.h"
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#include "ec/google/chromeec/ec.h"
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#include <cbfs.h>
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#include <cbfs.h>
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@ -23,6 +23,7 @@
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include "superio.h"
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#include "superio.h"
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#include "thermal.h"
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#include "thermal.h"
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@ -23,6 +23,7 @@
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#else
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#else
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#endif
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#endif
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#include <southbridge/intel/bd82x6x/pch.h>
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#if !CONFIG(USE_NATIVE_RAMINIT)
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#if !CONFIG(USE_NATIVE_RAMINIT)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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#include <drivers/intel/gma/libgfxinit.h>
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#include <drivers/intel/gma/libgfxinit.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include <drivers/intel/gma/opregion.h>
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#include <drivers/intel/gma/opregion.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <cbmem.h>
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#include <cbmem.h>
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#include "chip.h"
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#include "chip.h"
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@ -29,6 +29,7 @@
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#include <mrc_cache.h>
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#include <mrc_cache.h>
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#include <southbridge/intel/bd82x6x/me.h>
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#include <southbridge/intel/bd82x6x/me.h>
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#include <southbridge/intel/common/smbus.h>
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#include <southbridge/intel/common/smbus.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include "raminit_native.h"
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#include "raminit_native.h"
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@ -52,8 +52,6 @@
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#define IOMMU_BASE1 0xfed90000ULL
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#define IOMMU_BASE1 0xfed90000ULL
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#define IOMMU_BASE2 0xfed91000ULL
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#define IOMMU_BASE2 0xfed91000ULL
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#include <southbridge/intel/bd82x6x/pch.h>
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/* Everything below this line is ignored in the DSDT */
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/* Everything below this line is ignored in the DSDT */
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#ifndef __ACPI__
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#ifndef __ACPI__
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#include <cpu/intel/model_206ax/model_206ax.h>
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#include <cpu/intel/model_206ax/model_206ax.h>
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*/
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*/
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/* Intel Cougar Point PCH support */
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/* Intel Cougar Point PCH support */
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#include <southbridge/intel/bd82x6x/pch.h>
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Scope(\)
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Scope(\)
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{
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{
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