inteltool/ahci: Add Skylake support
The SATA device moved from 0:1f.2 to 0:17.0, 0:1f.2 became PMC. We detect that by checking the PCI device class. The ABAR MMIO space has grown to 2KiB and up to 8 ports are supported now. For backwards compatibility, only dump port registers of ports that are enabled in the Ports Implemented (PI) register. Change-Id: I8e0f07d7359d92f689882b5afefa5ffb3766ee8b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -2,6 +2,7 @@
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* ahci.c: dump AHCI registers
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*
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* Copyright (C) 2016 Iru Cai
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* Copyright (C) 2017 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -19,9 +20,6 @@
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#include <inttypes.h>
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#include "inteltool.h"
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#define NUM_SATA_PORTS 6
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#define MMIO_SIZE 0x400
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static const char *ghc_regs[] = {
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"CAP", "GHC", "IS", "PI",
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"VS", "CCC_CTL", "CCC_PORTS", "EM_LOC",
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@ -41,17 +39,24 @@ static const char *port_ctl_regs[] = {
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int print_ahci(struct pci_dev *ahci)
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{
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uint64_t mmio_phys;
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size_t mmio_size;
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uint8_t *mmio;
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uint32_t i, j;
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if (!ahci) {
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puts("No SATA device found");
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return 0;
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}
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printf("\n============= AHCI Registers ==============\n\n");
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mmio_phys = ahci->base_addr[5] & ~0x7ULL;
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if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA)
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mmio_size = 0x800;
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else
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mmio_size = 0x400;
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const pciaddr_t mmio_phys = ahci->base_addr[5] & ~0x7ULL;
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printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)mmio_phys);
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mmio = map_physical(mmio_phys, MMIO_SIZE);
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mmio = map_physical(mmio_phys, mmio_size);
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if (mmio == NULL) {
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perror("Error mapping MMIO");
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exit(1);
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@ -63,15 +68,27 @@ int print_ahci(struct pci_dev *ahci)
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(i / 4 < NUM_GHC) ? ghc_regs[i / 4]:"Reserved");
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}
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for (i = 0; i < NUM_SATA_PORTS; i++) {
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printf("\nPort %d Control Registers:\n", i);
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uint8_t *mmio_port = mmio + 0x100 + i * 0x80;
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for (j = 0; j < 0x80; j += 4) {
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printf("0x%03x: 0x%08x (%s)\n", 0x100+i*0x80+j, *(uint32_t *)(mmio_port + j),
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(j / 4 < NUM_PORTCTL) ? port_ctl_regs[j / 4]:"Reserved");
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const size_t max_ports = (mmio_size - 0x100) / 0x80;
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for (i = 0; i < max_ports; i++) {
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if (*(uint32_t *)(mmio + 0x0c) & 1 << i) {
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printf("\nPort %d Control Registers:\n", i);
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uint8_t *mmio_port = mmio + 0x100 + i * 0x80;
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for (j = 0; j < 0x80; j += 4) {
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printf("0x%03x: 0x%08x (%s)\n", 0x100+i*0x80+j,
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*(uint32_t *)(mmio_port + j),
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(j / 4 < NUM_PORTCTL) ?
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port_ctl_regs[j / 4] :
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"Reserved");
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}
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}
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}
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unmap_physical((void *)mmio, MMIO_SIZE);
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if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA) {
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puts("\nOther registers:");
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for (i = 0x500; i < mmio_size; i += 4)
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printf("0x%03x: 0x%08x\n", i, *(uint32_t *)(mmio + i));
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}
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unmap_physical((void *)mmio, mmio_size);
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return 0;
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}
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@ -4,6 +4,7 @@
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* Copyright (C) 2008-2010 by coresystems GmbH
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* written by Stefan Reinauer <stepan@coresystems.de>
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* Copyright (C) 2009 Carl-Daniel Hailfinger
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* Copyright (C) 2017 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -457,17 +458,24 @@ int main(int argc, char *argv[])
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gfx = 0;
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}
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if (sb->device_id == PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC)
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if (sb->device_id == PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC) {
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ahci = pci_get_dev(pacc, 0, 0, 0x13, 0);
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else
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} else {
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ahci = pci_get_dev(pacc, 0, 0, 0x1f, 2);
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if (ahci) {
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pci_fill_info(ahci, PCI_FILL_CLASS);
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if (ahci->device_class != PCI_CLASS_STORAGE_SATA)
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ahci = pci_get_dev(pacc, 0, 0, 0x17, 0);
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}
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}
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if (ahci) {
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pci_fill_info(ahci, PCI_FILL_IDENT | PCI_FILL_BASES |
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PCI_FILL_CLASS);
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if (ahci->vendor_id != PCI_VENDOR_ID_INTEL)
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ahci = 0;
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if (ahci->vendor_id != PCI_VENDOR_ID_INTEL ||
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ahci->device_class != PCI_CLASS_STORAGE_SATA)
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ahci = NULL;
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}
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id = cpuid(1);
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@ -136,6 +136,7 @@ static inline uint32_t inl(unsigned port)
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102
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#define PCI_DEVICE_ID_INTEL_CM236 0xa150
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
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