mb/google/deltaur: Remove mainboard from tree
This board never made it to production, and development on it has long since stopped; it is a maintenance burden, therefore drop it from the tree. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Tim Wawrzynczak
Felix Singer
parent
35f73bcce1
commit
da958d679d
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@ -73,8 +73,6 @@
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- Ultima (Lenovo Yoga 11e G3)
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- Wizpig
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- Daisy (Samsung Chromebook (2012))
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- Deltan
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- Deltaur
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- Drallion
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- Eve (Google Pixelbook)
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- Fizz
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@ -1,86 +0,0 @@
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config BOARD_GOOGLE_BASEBOARD_DELTAUR
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_ISH
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select EC_GOOGLE_WILCO
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select I2C_TPM
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_USES_IFD_EC_REGION
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_TIGERLAKE
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select SYSTEM_TYPE_LAPTOP
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select TPM_GOOGLE_CR50
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config BOARD_GOOGLE_DELTAN
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select BOARD_GOOGLE_BASEBOARD_DELTAUR
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select MAINBOARD_USES_IFD_GBE_REGION
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config BOARD_GOOGLE_DELTAUR
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select BOARD_GOOGLE_BASEBOARD_DELTAUR
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if BOARD_GOOGLE_BASEBOARD_DELTAUR
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config CHROMEOS
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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config DEVICETREE
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default "variants/baseboard/devicetree.cb"
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x3
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x50
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-gbe.fmd" if BOARD_GOOGLE_DELTAN
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_GOOGLE_DELTAUR
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config POWER_OFF_ON_CR50_UPDATE
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bool
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default n
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config MAINBOARD_DIR
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default "google/deltaur"
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config MAINBOARD_FAMILY
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string
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default "Google_Deltaur"
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config MAINBOARD_PART_NUMBER
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default "Deltan" if BOARD_GOOGLE_DELTAN
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default "Deltaur" if BOARD_GOOGLE_DELTAUR
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 23 # GPE0_DW0_23 (GPP_C23)
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config UART_FOR_CONSOLE
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int
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default 2
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config VARIANT_DIR
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default "deltan" if BOARD_GOOGLE_DELTAN
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default "deltaur" if BOARD_GOOGLE_DELTAUR
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config VBOOT
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select HAS_RECOVERY_MRC_CACHE
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select VBOOT_LID_SWITCH
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endif # BOARD_GOOGLE_BASEBOARD_DELTAUR
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@ -1,7 +0,0 @@
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comment "Deltaur"
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config BOARD_GOOGLE_DELTAN
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bool "-> Deltan"
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config BOARD_GOOGLE_DELTAUR
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bool "-> Deltaur"
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@ -1,26 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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bootblock-y += ec.c
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romstage-y += romstage.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += ec.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-y += ec.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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subdirs-y += spd
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@ -1,6 +0,0 @@
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Vendor name: Google
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Board name: Deltaur
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -1,22 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <ec/google/wilco/bootblock.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static void early_config_gpio(void)
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{
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const struct pad_config *early_gpio_table;
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size_t num_gpios = 0;
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early_gpio_table = variant_early_gpio_table(&num_gpios);
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gpio_configure_pads(early_gpio_table, num_gpios);
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}
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void bootblock_mainboard_init(void)
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{
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early_config_gpio();
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wilco_ec_early_init();
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}
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@ -1,49 +0,0 @@
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x606000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x100000
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SI_GBE(PRESERVE)@0x101000 0x2000
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SI_ME@0x103000 0x4ff000
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SI_PDR(PRESERVE)@0x602000 0x4000
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}
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SI_BIOS@0x606000 0x19fa000 {
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RW_DIAG@0x0 0x9fa000 {
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RW_LEGACY(CBFS)@0x0 0x9ea000
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DIAG_NVRAM@0x9ea000 0x10000
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}
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RW_SECTION_A@0x10ca000 0x280000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x26ffc0
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RW_FWID_A@0x27ffc0 0x40
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}
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RW_SECTION_B@0x134a000 0x280000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x26ffc0
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RW_FWID_B@0x27ffc0 0x40
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}
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RW_MISC@0x15ca000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG(PRESERVE)@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x28000 0x2000
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RW_NVRAM(PRESERVE)@0x2a000 0x6000
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}
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WP_RO@0x15fa000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x3f0000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0x3000
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COREBOOT(CBFS)@0x4000 0x3ec000
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}
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}
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}
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}
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@ -1,96 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <security/tpm/tss.h>
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#include <device/device.h>
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#include <intelblocks/pmclib.h>
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#include <soc/pmc.h>
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#include <soc/pci_devs.h>
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enum rec_mode_state {
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REC_MODE_UNINITIALIZED,
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REC_MODE_NOT_REQUESTED,
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REC_MODE_REQUESTED,
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};
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{-1, ACTIVE_HIGH, 0, "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_write_protect_state(void)
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{
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return gpio_get(GPIO_PCH_WP);
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}
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static bool raw_get_recovery_mode_switch(void)
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{
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return !gpio_get(GPIO_REC_MODE);
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}
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int get_recovery_mode_switch(void)
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{
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static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED;
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enum rec_mode_state state = REC_MODE_NOT_REQUESTED;
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uint8_t cr50_state = 0;
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/* Check cached state, since TPM will only tell us the first time */
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if (saved_rec_mode != REC_MODE_UNINITIALIZED)
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return saved_rec_mode == REC_MODE_REQUESTED;
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/*
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* Read one-time recovery request from cr50 in verstage only since
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* the TPM driver won't be set up in time for other stages like romstage
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* and the value from the TPM would be wrong anyway since the verstage
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* read would have cleared the value on the TPM.
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*
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* The TPM recovery request is passed between stages through vboot data
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* or cbmem depending on stage.
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*/
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if (ENV_SEPARATE_VERSTAGE &&
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tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS &&
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cr50_state)
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state = REC_MODE_REQUESTED;
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/* Read state from the GPIO controlled by servo. */
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if (raw_get_recovery_mode_switch())
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state = REC_MODE_REQUESTED;
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/* Store the state in case this is called again in verstage. */
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saved_rec_mode = state;
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return state == REC_MODE_REQUESTED;
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}
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int get_lid_switch(void)
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{
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return 1;
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}
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void mainboard_prepare_cr50_reset(void)
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{
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/* Ensure system powers up after CR50 reset */
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if (ENV_RAMSTAGE)
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pmc_soc_set_afterg3_en(true);
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}
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int get_ec_is_trusted(void)
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{
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/* Do not have a Chrome EC involved in entering recovery mode;
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Always return trusted. */
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return 1;
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}
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@ -1,48 +0,0 @@
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x606000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x100000
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SI_ME@0x101000 0x501000
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SI_PDR(PRESERVE)@0x602000 0x4000
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}
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SI_BIOS@0x606000 0x19fa000 {
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RW_DIAG@0x0 0x9fa000 {
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RW_LEGACY(CBFS)@0x0 0x9ea000
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DIAG_NVRAM@0x9ea000 0x10000
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}
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RW_SECTION_A@0x10ca000 0x280000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x26ffc0
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RW_FWID_A@0x27ffc0 0x40
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}
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RW_SECTION_B@0x134a000 0x280000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x26ffc0
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RW_FWID_B@0x27ffc0 0x40
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}
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RW_MISC@0x15ca000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG(PRESERVE)@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x28000 0x2000
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RW_NVRAM(PRESERVE)@0x2a000 0x6000
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}
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WP_RO@0x15fa000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x3f0000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0x3000
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COREBOOT(CBFS)@0x4000 0x3ec000
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}
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}
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}
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}
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@ -1,43 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include "variant/ec.h"
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#include "variant/gpio.h"
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/tigerlake/acpi/southbridge.asl>
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#include <soc/intel/tigerlake/acpi/tcss.asl>
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}
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}
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/wilco/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/wilco/acpi/ec.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -1,10 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <console/console.h>
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#include <ec/google/wilco/commands.h>
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#include <variant/ec.h>
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void mainboard_post(uint8_t value)
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{
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wilco_ec_save_post_code(value);
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}
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include "baseboard/hda_verb.h"
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@ -1,22 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static void mainboard_chip_init(void *chip_info)
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{
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const struct pad_config *base_pads;
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const struct pad_config *override_pads;
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size_t base_num, override_num;
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base_pads = variant_base_gpio_table(&base_num);
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override_pads = variant_override_gpio_table(&override_num);
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gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_chip_init,
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};
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@ -1,9 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <soc/romstage.h>
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|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
variant_memory_init(mupd);
|
||||
}
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/google/wilco/smm.h>
|
||||
#include <intelblocks/smihandler.h>
|
||||
#include <variant/ec.h>
|
||||
|
||||
void mainboard_smi_espi_handler(void)
|
||||
{
|
||||
wilco_ec_smi_espi();
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
wilco_ec_smi_sleep(slp_typ);
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
wilco_ec_smi_apmc(apmc);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
bootblock-y += gpio.c
|
||||
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += sku.c
|
||||
|
||||
verstage-y += gpio.c
|
||||
|
|
@ -1,298 +0,0 @@
|
|||
chip soc/intel/tigerlake
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
|
||||
# TODO: Figure out GPE DW1&2
|
||||
register "pmc_gpe0_dw0" = "GPP_C"
|
||||
register "pmc_gpe0_dw1" = "GPP_E"
|
||||
#register "pmc_gpe0_dw2" = "??"
|
||||
|
||||
# Wilco EC host command ranges
|
||||
register "gen1_dec" = "0x00040931" # 0x930-0x937
|
||||
register "gen2_dec" = "0x00040941" # 0x940-0x947
|
||||
register "gen3_dec" = "0x000c0951" # 0x950-0x95f
|
||||
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
# TODO: not yet
|
||||
register "dptf_enable" = "0"
|
||||
|
||||
register "tcc_offset" = "0"
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "SaGv_Disabled"
|
||||
|
||||
register "SataSalpSupport" = "1"
|
||||
|
||||
# TODO: the lengths are all MID for right now.
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 2
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Ext USB Port 1 (Right)
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Ext USB Port 2 (Left)
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 3042 (WWAN)
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
|
||||
|
||||
# PCIe root port 7 (Card Reader), clock 4
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieClkSrcUsage[4]" = "6"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
|
||||
# PCIe root port 9 (NVMe), clock 2
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "8"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
register "PcieRpSlotImplemented[8]" = "1"
|
||||
|
||||
# Mark unused SRCCLKREQs as so
|
||||
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| I2C0 | Touchscreen |
|
||||
#| I2C1 | Touchpad |
|
||||
#| I2C2 | ISH ? |
|
||||
#| I2C3 | cr50 TPM |
|
||||
#| I2C5 | ISH ? |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.early_init = 1,
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
}"
|
||||
|
||||
register "SerialIoI2cMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "SerialIoUartMode" = "{
|
||||
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "SerialIoGSpiMode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
# HD Audio
|
||||
register "PchHdaAudioLinkHdaEnable" = "1"
|
||||
register "PchHdaIDispCodecDisconnect" = "1"
|
||||
|
||||
# TCSS USB3
|
||||
register "TcssXhciEn" = "1"
|
||||
|
||||
# DisplayPort
|
||||
register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
|
||||
register "DdiPortAHpd" = "1"
|
||||
|
||||
# Disable PM to allow for shorter irq pulses
|
||||
register "gpio_override_pm" = "1"
|
||||
register "gpio_pm[0]" = "0"
|
||||
register "gpio_pm[1]" = "0"
|
||||
register "gpio_pm[2]" = "0"
|
||||
register "gpio_pm[3]" = "0"
|
||||
register "gpio_pm[4]" = "0"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Graphics
|
||||
device pci 04.0 off end # DPTF
|
||||
device pci 05.0 off end # IPU
|
||||
device pci 06.0 off end # PEG60
|
||||
device pci 07.0 on end # TBT_PCIe0
|
||||
device pci 07.1 on end # TBT_PCIe0
|
||||
device pci 07.2 on end # TBT_PCIe0
|
||||
device pci 07.3 on end # TBT_PCIe0
|
||||
device pci 08.0 on end # GNA
|
||||
device pci 09.0 off end # NPK
|
||||
device pci 0a.0 off end # Crash-log SRAM
|
||||
device pci 0d.0 on end # USB xHCI
|
||||
device pci 0d.1 off end # USB xDCI
|
||||
device pci 0d.2 off end # TBT DMA0
|
||||
device pci 0d.3 off end # TBT DMA1
|
||||
device pci 0e.0 off end # VMD
|
||||
|
||||
device pci 10.0 off end # THC #0
|
||||
device pci 10.1 off end # THC #1
|
||||
device pci 10.2 on end # CNVi Bluetooth
|
||||
device pci 11.0 off end # UART #3
|
||||
device pci 11.1 off end # UART4
|
||||
device pci 11.2 off end # UART5
|
||||
device pci 11.3 off end # UART6
|
||||
|
||||
device pci 12.0 on end # ISH
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 13.0 off end # GSPI #3
|
||||
device pci 13.1 off end # GSPI #4
|
||||
device pci 13.2 off end # GSPI #5
|
||||
device pci 13.3 off end # GSPI #6
|
||||
|
||||
device pci 14.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Root Hub""
|
||||
register "type" = "UPC_TYPE_HUB"
|
||||
device usb 0.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Type-C Port 1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 2.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Type-C Port 2""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device usb 2.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Type-A Port 1 (Right)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 2)"
|
||||
device usb 2.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Type-A Port 2 (Left)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 2.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""M.2 3042 (WWAN)""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USH""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""M.2 2230 (BT)""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
|
||||
device usb 2.9 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Type-A Port 1""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 3.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Type-A Port 2""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device usb 3.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 3.2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # USB 3.2 2x1 xHCI HC
|
||||
|
||||
device pci 14.1 off end # USB 3.2 1x1 xDCI HC
|
||||
device pci 14.2 on end # Shared SRAM
|
||||
|
||||
device pci 14.3 on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # CNVi WiFi
|
||||
|
||||
device pci 15.0 on end # I2C #0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 on end # I2C #2
|
||||
device pci 15.3 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end # I2C #3
|
||||
|
||||
device pci 16.0 on end # HECI #1
|
||||
device pci 16.1 off end # HECI #2
|
||||
device pci 16.2 off end # IDE-R
|
||||
device pci 16.3 off end # KT-T
|
||||
device pci 16.4 on end # HECI #3
|
||||
device pci 16.5 on end # HECI #4
|
||||
device pci 17.0 on end # SATA (AHCI)
|
||||
device pci 19.0 off end # I2C #4
|
||||
device pci 19.1 on end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
|
||||
device pci 1c.0 on end # PCIe Root Port #1 (USB)
|
||||
device pci 1c.1 on end # PCIe Root Port #2 (USB)
|
||||
device pci 1c.2 off end # PCIe Root Port #3 ()
|
||||
device pci 1c.3 off end # PCIe Root Port #4 (WWAN)
|
||||
device pci 1c.4 on end # PCIe Root Port #5 (LTE)
|
||||
device pci 1c.5 off end # PCIe Root Port #6 (WiFi)
|
||||
device pci 1c.6 on end # PCIe Root Port #7 (Card reader)
|
||||
device pci 1c.7 on end # PCIe Root Port #8 (LAN)
|
||||
device pci 1d.0 on end # PCIe Root Port #9 (NVMe)
|
||||
device pci 1d.1 off end # PCIe Root Port #10 (NVMe)
|
||||
device pci 1d.2 off end # PCIe Root Port #11 (NVMe)
|
||||
device pci 1d.3 off end # PCIe Root Port #12 (NVMe)
|
||||
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
|
||||
device pci 1f.0 on
|
||||
chip ec/google/wilco
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end # eSPI
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 hidden end # PMC
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 off end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI Flash Controller
|
||||
device pci 1f.6 off end # GbE Controller
|
||||
device pci 1f.7 off end # Intel Trace Hub
|
||||
end
|
||||
end
|
||||
|
|
@ -1,429 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <baseboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <variant/gpio.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* A0 thru A6 are ESPI, configured elsewhere */
|
||||
/* A0 : ESPI_IO0 ==> ESPI_IO_0 */
|
||||
/* A1 : ESPI_IO1 ==> ESPI_IO_1 */
|
||||
/* A2 : ESPI_IO2 ==> ESPI_IO_2 */
|
||||
/* A3 : ESPI_IO3 ==> ESPI_IO_3 */
|
||||
/* A4 : ESPI_CS# ==> ESPI_CS_L */
|
||||
/* A5 : ESPI_CLK ==> ESPI_CLK */
|
||||
/* A6 : ESPI_RESET# ==> NC(TP764) */
|
||||
/* A7 : GPP_A7 ==> CNVI_EN# */
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
/* A8 : GPP_A8 ==> CNV_RF_RESET# */
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
|
||||
/* A9 : GPP_A9 ==> CLKREQ_CNV#_1P8 */
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2),
|
||||
/* A10 : GPP_A10 ==> TOUCH_SCREEN_RST# */
|
||||
PAD_CFG_GPO(GPP_A10, 0, DEEP),
|
||||
/* A11 : GPP_A11 ==> NC */
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
/* A12 : GPP_A12 ==> M2280_PCIE_SATA# */
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
/* A13 : GPP_A13 ==> PCH_BT_RADIO_DIS# */
|
||||
PAD_CFG_GPO(GPP_A13, 1, DEEP),
|
||||
/* A14 : GPP_A14 ==> USB_OC1# */
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
/* A15 : GPP_A15 ==> USB_OC2# */
|
||||
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
/* A16 : GPP_A16 ==> USB_OC3# */
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
/* A17 : GPP_A17 ==> NC */
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
/* A18 : GPP_A18 ==> HDMI_HPD */
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
/* A19 : GPP_A19 ==> NC */
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
/* A20 : GPP_A20 ==> NC */
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
/* A21 : GPP_A21 ==> 3.3V_CAM_EN# */
|
||||
PAD_CFG_GPO(GPP_A21, 0, PLTRST),
|
||||
/* A22 : GPP_A22 ==> KB_DET# */
|
||||
PAD_CFG_GPI(GPP_A22, NONE, PLTRST),
|
||||
/* A23 : GPP_A23 ==> RECOVERY# */
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
|
||||
/* B0 : GPP_B0 ==> CORE_VID0 */
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
/* B1 : GPP_B1 ==> CORE_VID1 */
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
/* B2 : GPP_B2 ==> VRALERT_L */
|
||||
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
|
||||
/* B3 : GPP_B3 ==> TOUCH_SCREEN_PD# */
|
||||
PAD_CFG_GPO(GPP_B3, 0, PLTRST),
|
||||
/* B4 : GPP_B4 ==> TOUCH_SCREEN_DET# */
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
/* B5 : GPP_B5 ==> ISH_I2C0_SDA */
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
/* B6 : GPP_B6 ==> ISH_I2C0_SCL */
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
|
||||
/* B7 : GPP_B7 ==> NC */
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
/* B8 : GPP_B8 ==> NC */
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
/* B9 : GPP_B9 ==> NC */
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
/* B10 : GPP_B10 ===> NC */
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
/* B11 : GPP_B11 ==> TBT_I2C_INT# */
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
|
||||
/* B12 : GPP_B12 ==> SIO_SLP_S0# */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* B13 : PLTRST# ==> PCH_PLTRST# */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* B14 : GPP_B14 ==> SPKR (PIN STRAP, Top Swap Override) */
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
/* B15 : GPP_B15 ==> SPK_DET0# */
|
||||
PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
|
||||
/* B16 : GPP_B16 ==> ONE_DIMM# */
|
||||
PAD_CFG_GPI(GPP_B16, NONE, PLTRST),
|
||||
/* B17 : GPP_B17 ==> HOST_SD_WP# */
|
||||
PAD_CFG_GPO(GPP_B17, 0, PLTRST),
|
||||
/* B18 : GPP_B18 ==> NRB_BIT (PIN STRAP, No Reboot) */
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
/* B19 : GPP_B19 ==> D3_RST# */
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
/* B20 : GPP_B20 ==> LCD_CBL_DET# */
|
||||
PAD_CFG_GPI(GPP_B20, NONE, PLTRST),
|
||||
/* B21 : GPP_B21 ==> PCH_TOUCH_SCREEN_EN */
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
/* B22 : GPP_B22 ==> NC */
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
/* B23 : GPP_B23 ==> NC (PIN STRAP, CPUNSSC frequency) */
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
|
||||
/* C0 : GPP_C0 ==> MEM_SMBCLK */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* C1 : GPP_C1 ==> MEM_SMBDATA */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
/* C2 : GPP_C2 ==> NC (PIN STRAP, TLS Confidentiality) */
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
/* C3 : GPP_C3 ==> SML0_SMBCLK */
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
/* C4 : GPP_C4 ==> SML0_SMBDATA */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
/* C5 : GPP_C5 ==> NC (PIN STRAP, Boot Strap 0) */
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
/* C6 : GPP_C6 ==> SML1_SMBCLK */
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
/* C7 : GPP_C7 ==> SML1_SMBDATA */
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
/* C8 : GPP_C8 ==> WWAN_FULL_POWER_EN */
|
||||
PAD_CFG_GPO(GPP_C8, 1, DEEP),
|
||||
/* C9 : GPP_C9 ==> SBIOS_TX */
|
||||
PAD_CFG_GPO(GPP_C9, 0, PLTRST),
|
||||
/* C10 : GPP_C10 ==> NC */
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
/* C11 : GPP_C11 ==> NC */
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
/* C12 : GPP_C12 ==> NC */
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
/* C13 : GPP_C13 ==> PCH_SSD_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_C13, 1, DEEP),
|
||||
/* C14 : GPP_C14 ==> NC */
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
/* C15 : GPP_C15 ==> NC */
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
/* C16 : GPP_C16 ==> I2C0_SDA_TS */
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
/* C17 : GPP_C17 ==> I2C0_SCL_TS */
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
/* C18 : GPP_C18 ==> I2C1_SDA_TP */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
/* C19 : GPP_C19 ==> I2C1_SCL_TP */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
/* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
/* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
/* C22 : GPP_C22 ==> H1_FLASH_WP */
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
/* C23 : GPP_C23 ==> H1_PCH_INT# */
|
||||
PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT),
|
||||
|
||||
/* D0 : GPP_D0 ==> ISH_ACC1_INT */
|
||||
PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
|
||||
/* D1 : GPP_D1 ==> ISH_ACC2_INT */
|
||||
PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
|
||||
/* D2 : GPP_D2 ==> ISH_TABLE_MODE# */
|
||||
PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
|
||||
/* D3 : GPP_D3 ==> ISH_ALS_INT# */
|
||||
PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
|
||||
/* D4 : GPP_D4 ==> RT_FORCE_PWR */
|
||||
PAD_CFG_GPO(GPP_D4, 0, PLTRST),
|
||||
/* D5 : GPP_D5 ==> CLKREQ_PCIE#0 */
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
/* D6 : GPP_D6 ==> CLKREQ_PCIE#1 */
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
/* D7 : GPP_D7 ==> CLKREQ_PCIE#2 */
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
/* D8 : GPP_D8 ==> CLKREQ_PCIE#3 */
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
/* D9 : GPP_D9 ==> TBT_2_LSX_TX */
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
|
||||
/* D10 : GPP_D10 ==> TBT_2_LSX_RX */
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
|
||||
/* D11 : GPP_D11 ==> TBT_3_LSX_TX */
|
||||
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4),
|
||||
/* D12 : GPP_D12 ==> TBT_3_LSX_RX */
|
||||
PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF4),
|
||||
/* D13 : GPP_D13 ==> SML0B_SMLDATA */
|
||||
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
|
||||
/* D14 : GPP_D14 ==> SML0B_SMLCLK */
|
||||
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2),
|
||||
/* D15 : GPP_D15 ==> NC */
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
/* D16 : GPP_D16 ==> SML0BALERT# */
|
||||
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
|
||||
/* D17 : GPP_D17 ==> ISH_NB_MODE# */
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
/* D18 : GPP_D18 ==> ISH_LID_CL#_NB */
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
/* D19 : GPP_D19 ==> NC */
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
|
||||
/* E0 : GPP_E0 ==> NC */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
/* E1 : GPP_E1 ==> TOUCH_SCREEN_INT# */
|
||||
PAD_CFG_GPI_APIC(GPP_E1, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* E2 : GPP_E2 ==> MEDIACARD_IRQ# */
|
||||
PAD_CFG_GPI_APIC(GPP_E2, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* E3 : GPP_E3 ==> MEM_INTERLEAVED */
|
||||
PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
|
||||
/* E4 : GPP_E4 ==> NC */
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
/* E5 : GPP_E5 ==> M2280_DEVSLP */
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
/* E6 : GPP_E6 ==> (PIN STRAP, Reserved) */
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
/* E7 : CPU_GP1 ==> PCH_TOUCHPAD_INTR# */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_E7, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* E8 : GPP_E8 ==> SECURE_BIO */
|
||||
PAD_CFG_GPO(GPP_E8, 0, PLTRST),
|
||||
/* E9 : GPP_E9 ==> OC0# */
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* E10 : GPP_E10 ==> HDMI_PD# */
|
||||
PAD_CFG_GPO(GPP_E10, 1, DEEP),
|
||||
/* E11 : GPP_E11 ==> VPRO_DET# */
|
||||
PAD_CFG_GPI(GPP_E11, NONE, PLTRST),
|
||||
/* E12 : GPP_E12 ==> RTC_DET# */
|
||||
PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
|
||||
/* E13 : GPP_E13 ==> TBT_DET# */
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
/* E14 : GPP_E14 ==> EPD_HPD */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* E15 : GPP_E15 ==> ISH_LID_CL#_TAB */
|
||||
PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
|
||||
/* E16 : GPP_E16 ==> NC */
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
/* E17 : GPP_E17 ==> NC */
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
/* E18 : GPP_E18 ==> TBT_LSX0_TXD */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
|
||||
/* E19 : GPP_E19 ==> TBT_LSX0_RXD */
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
|
||||
/* E20 : GPP_E20 ==> TBT_LSX1_TXD */
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
|
||||
/* E21 : GPP_E21 ==> TBT_LSX1_RXD */
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
|
||||
/* E22 : GPP_E22 ==> NC */
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
/* E23 : GPP_E23 ==> NC */
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* F0 : GPP_F0 ==> BRI_DT_1P8 */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
/* F1 : GPP_F1 ==> CNV_BRI_RSP_1P8 */
|
||||
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||
/* F2 : GPP_F2 ==> CNV_RGI_DT_1P8 */
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
/* F3 : GPP_F3 ==> CNV_RGI_RSP_1P8 */
|
||||
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
|
||||
/* F4 : GPP_F4 ==> NC */
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
/* F5 : GPP_F5 ==> NC */
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
/* F6 : GPP_F6 ==> NC */
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
/* F7 : GPP_F7 ==> NC (PIN STRAP, Reserved) */
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
/* F8 : GPP_F8 ==> NC */
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
/* F9 : GPP_F9 ==> NC */
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
/* F10 : GPP_F10 ==> NC (PIN STRAP, Reserved) */
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
/* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
/* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
/* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
/* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
/* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
/* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */
|
||||
PAD_CFG_GPO(GPP_F16, 1, DEEP),
|
||||
/* F17 : GPP_F17 ==> WWAN_GPIO_PERST# */
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
/* F18 : GPP_F18 ==> WWAN_GPIO_WAKE# */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
|
||||
/* F19 : GPP_F19 ==> CAM_MIC_CBL_DET# */
|
||||
PAD_CFG_GPI(GPP_F19, NONE, PLTRST),
|
||||
/* F20 : GPP_F20 ==> NC */
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
/* F21 : GPP_F21 ==> NC */
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
/* F22 : VNN_CTRL */
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
/* F23 : V1P05_CTRL */
|
||||
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
|
||||
|
||||
/* H0 : GPPH0_BOOT_STRAP1 */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
/* H1 : GPPH1_BOOT_STRAP2 */
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
/* H2 : GPPH2_BOOT_STRAP3 */
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
/* H3 : GPP_H3 ==> NC */
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
/* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
/* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
/* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/* H8 : GPP_H8 ==> NC */
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
/* H9 : GPP_H9 ==> NC */
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
/* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
/* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
|
||||
/* H12 : GPP_H12 ==> NC */
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
/* H13 : GPP_H13 ==> NC */
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
/* H14 : GPP_H14 ==> NC */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* H15 : GPP_H15 ==> NC */
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
/* H16 : GPP_H16 ==> CPU_DPB_CTRL_CLK */
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
/* H17 : GPP_H17 ==> CPU_DPB_CTRL_DATA */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
/* H18 : CPU_C10_GATE# ==> CPU_C10_GATE# */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* H19 : GPP_H19 ==> NC */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
/* H20 : GPP_H20 ==> NC */
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
/* H21 : GPP_H21 ==> NC */
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
/* H22 : GPP_H22 ==> NC */
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
/* H23 : GPP_H23 ==> NC */
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* R0 : GPP_R0 ==> HDA_BCLK */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
/* R1 : GPP_R1 ==> HDA_SYNC */
|
||||
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
|
||||
/* R2 : GPP_R2 ==> HDA_SDO (PIN STRAP, Flash Descriptor Security Override */
|
||||
PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
|
||||
/* R3 : GPP_R3 ==> HDA_SDIO */
|
||||
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
|
||||
/* R4 : GPP_R4 ==> HDA_RST# */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
/* R5 : GPP_R5 ==> NC */
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
/* R6 : GPP_R6 ==> SD_PWR_EN1 */
|
||||
PAD_CFG_GPO(GPP_R6, 0, PLTRST),
|
||||
/* R7 : GPP_R7 ==> SD_PWR_EN2 */
|
||||
PAD_CFG_GPO(GPP_R7, 0, PLTRST),
|
||||
|
||||
/* S0 : GPP_S0 ==> NC */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
/* S1 : GPP_S1 ==> NC */
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
/* S2 : GPP_S2 ==> NC */
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
/* S3 : GPP_S3 ==> NC */
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
/* S4 : GPP_S4 ==> NC */
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
/* S5 : GPP_S5 ==> NC */
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
/* S6 : GPP_S6 ==> NC */
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
/* S7 : GPP_S7 ==> NC */
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* GPD0: GPD0 ==> PCH_BATLOW# */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1: GPD1 ==> AC_PRESENT */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2: GPD2 ==> LAN_WAKE# */
|
||||
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* GPD3: GPD3 ==> SIO_PWRBTN# */
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
/* GPD4: GPD4 ==> SIO_SLP_S3# */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5: GPD5 ==> SIO_SLP_S4# */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6: GPD6 ==> SIO_SLP_A# */
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7: GPD7 ==> PCH_TBT_PERST# (PIN STRAP, Reserved) */
|
||||
PAD_CFG_GPO(GPD7, 0, PLTRST),
|
||||
/* GPD8: GPD8 ==> SUSCLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9: GPD9 ==> SIO_SLP_WLAN# */
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* GPD10: GPD10 ==> SIO_SLP_S5# */
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* GPD11: GPD11 ==> PM_LANPHY_EN */
|
||||
PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
const struct pad_config *__weak variant_base_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
DECLARE_WEAK_CROS_GPIOS(cros_gpios);
|
||||
|
||||
/* Weak implementation of overrides */
|
||||
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
|
||||
{
|
||||
*num = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Weak implementation of early gpio */
|
||||
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int __weak has_360_sensor_board(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __MAINBOARD_EC_H__
|
||||
#define __MAINBOARD_EC_H__
|
||||
|
||||
/* Enable PS/2 keyboard */
|
||||
#define SIO_EC_ENABLE_PS2K
|
||||
|
||||
#endif /* __MAINBOARD_EC_H__ */
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Flash Write Protect */
|
||||
#define GPIO_PCH_WP GPP_C22
|
||||
|
||||
/* Recovery mode */
|
||||
#define GPIO_REC_MODE GPP_A23
|
||||
|
||||
/* DDR channel enable pin */
|
||||
#define DDR_CHA_EN GPP_H4
|
||||
#define DDR_CHB_EN GPP_H5
|
||||
|
||||
/* Memory configuration board straps */
|
||||
#define GPIO_MEM_CONFIG_0 GPP_F11
|
||||
#define GPIO_MEM_CONFIG_1 GPP_F12
|
||||
#define GPIO_MEM_CONFIG_2 GPP_F13
|
||||
#define GPIO_MEM_CONFIG_3 GPP_F14
|
||||
#define GPIO_MEM_CONFIG_4 GPP_F15
|
||||
|
||||
/* DQ Memory Interleaved */
|
||||
#define MEMORY_INTERLEAVED GPP_E3
|
||||
|
||||
const struct pad_config *override_gpio_table(size_t *num);
|
||||
const struct pad_config *override_early_gpio_table(size_t *num);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,196 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_HDA_VERB_H
|
||||
#define MAINBOARD_HDA_VERB_H
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0236, // Codec Vendor / Device ID: Realtek ALC3204
|
||||
0xffffffff, // Subsystem ID
|
||||
0x0000002b, // Number of jacks (NID entries)
|
||||
/* Rest Codec First */
|
||||
AZALIA_RESET(0x1),
|
||||
/* HDA Codec Subsystem ID Verb-table
|
||||
HDA Codec Subsystem ID : 0x10280A20 */
|
||||
0x00172020,
|
||||
0x0017210A,
|
||||
0x00172228,
|
||||
0x00172310,
|
||||
/* Pin Widget Verb-table */
|
||||
/* Widget node 0x01 : Widget Reset */
|
||||
0x0017FF00,
|
||||
0x0017FF00,
|
||||
0x0017FF00,
|
||||
0x0017FF00,
|
||||
/* Pin widget 0x12 - DMIC1-2 */
|
||||
0x01271C40,
|
||||
0x01271D01,
|
||||
0x01271EA6,
|
||||
0x01271F90,
|
||||
/* Pin widget 0x13 - DMIC3-4 */
|
||||
0x01371C00,
|
||||
0x01371D00,
|
||||
0x01371E00,
|
||||
0x01371F40,
|
||||
/* Pin widget 0x14 - FRONT (Port-D) */
|
||||
0x01471C10,
|
||||
0x01471D01,
|
||||
0x01471E17,
|
||||
0x01471F90,
|
||||
/* Pin widget 0x18 - MIC1 */
|
||||
0x01871CF0,
|
||||
0x01871D11,
|
||||
0x01871E11,
|
||||
0x01871F41,
|
||||
/* Pin widget 0x19 - MIC2 (Port-F) */
|
||||
0x01971C30,
|
||||
0x01971D10,
|
||||
0x01971Ea1,
|
||||
0x01971F02,
|
||||
/* Pin widget 0x1A - LINE1 (Port-C) */
|
||||
0x01A71CF0,
|
||||
0x01A71D11,
|
||||
0x01A71E11,
|
||||
0x01A71F41,
|
||||
/* Pin widget 0x1B - LINE2 (Port-E) */
|
||||
0x01B71CF0,
|
||||
0x01B71D11,
|
||||
0x01B71E11,
|
||||
0x01B71F41,
|
||||
/* Pin widget 0x1D - BEEP-IN */
|
||||
0x01D71C01,
|
||||
0x01D71D00,
|
||||
0x01D71E70,
|
||||
0x01D71F40,
|
||||
/* Pin widget 0x1E - S/PDIF-OUT1 (Define special SKU for driver) */
|
||||
0x01E71CF2,
|
||||
0x01E71D12,
|
||||
0x01E71E12,
|
||||
0x01E71F42,
|
||||
/* Pin widget 0x21 - HP-OUT (Port-I) */
|
||||
0x02171C20,
|
||||
0x02171D10,
|
||||
0x02171E21,
|
||||
0x02171F02,
|
||||
|
||||
/* RESET to D0 */
|
||||
0x00170500,
|
||||
0x00170500,
|
||||
0x00170500,
|
||||
0x00170500,
|
||||
/* RESET Register */
|
||||
0x0205001A,
|
||||
0x02048003,
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
/* ALC3204 default-1(Class D RESET) */
|
||||
0x0205003C,
|
||||
0x02040354,
|
||||
0x0205003C,
|
||||
0x02040314,
|
||||
/* ALC3204 default-2 */
|
||||
0x02050040,
|
||||
0x02049800,
|
||||
0x02050034,
|
||||
0x0204023C,
|
||||
/* ALC3204 Speaker output power - 4 ohm 2W (+12dB gain)
|
||||
+ Combo Jack TRS setting */
|
||||
0x02050038,
|
||||
0x02043901,
|
||||
0x02050045,
|
||||
0x02045089,
|
||||
/* H/W AGC setting-1 */
|
||||
0x02050016,
|
||||
0x02040C50,
|
||||
0x02050012,
|
||||
0x0204EBC2,
|
||||
/* H/W AGC setting-2 */
|
||||
0x02050013,
|
||||
0x0204401D,
|
||||
0x02050016,
|
||||
0x02044E50,
|
||||
/* Zero data + EAPD to verb-control */
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
0x02050010,
|
||||
0x02040020,
|
||||
/* Zero data */
|
||||
0x02050030,
|
||||
0x02048000,
|
||||
0x02050030,
|
||||
0x02048000,
|
||||
/* ALC3204 default-3 */
|
||||
0x05750003,
|
||||
0x05740DA3,
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
/* ALC3204 default-4 */
|
||||
0x0205001B,
|
||||
0x02040A4B,
|
||||
0x02050008,
|
||||
0x02046A6C,
|
||||
/* JD1 */
|
||||
0x02050009,
|
||||
0x0204E003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
/* Microphone + Array MIC security Disable +ADC clock Enable */
|
||||
0x0205000D,
|
||||
0x0204A020,
|
||||
0x02050005,
|
||||
0x02040700,
|
||||
/* Speaker Enable */
|
||||
0x0205000C,
|
||||
0x020401EF,
|
||||
0x0205000C,
|
||||
0x020401EF,
|
||||
/* EQ Bypass + EQ HPF cutoff 250Hz */
|
||||
0x05350000,
|
||||
0x0534201A,
|
||||
0x0535001d,
|
||||
0x05340800,
|
||||
/* EQ-2 */
|
||||
0x0535001e,
|
||||
0x05340800,
|
||||
0x05350003,
|
||||
0x05341EF8,
|
||||
/* EQ-3 */
|
||||
0x05350004,
|
||||
0x05340000,
|
||||
0x05450000,
|
||||
0x05442000,
|
||||
/* EQ-4 */
|
||||
0x0545001d,
|
||||
0x05440800,
|
||||
0x0545001e,
|
||||
0x05440800,
|
||||
/* EQ-5 */
|
||||
0x05450003,
|
||||
0x05441EF8,
|
||||
0x05450004,
|
||||
0x05440000,
|
||||
/* EQ Update */
|
||||
0x05350000,
|
||||
0x0534E01A,
|
||||
0x05350000,
|
||||
0x0534E01A,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
/* PCBeep pass through to NID14 for ePSA test-1 */
|
||||
0x02050036,
|
||||
0x02047717,
|
||||
0x02050036,
|
||||
0x02047717,
|
||||
/* PCBeep pass through to NID14 for ePSA test-2 */
|
||||
0x01470740,
|
||||
0x0143B000,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
||||
#endif
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __BASEBOARD_VARIANTS_H__
|
||||
#define __BASEBOARD_VARIANTS_H__
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/*
|
||||
* The next set of functions return the gpio table and fill in the number of
|
||||
* entries for each table.
|
||||
*/
|
||||
const struct pad_config *variant_base_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_override_gpio_table(size_t *num);
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void);
|
||||
void variant_memory_init(FSPM_UPD *mupd);
|
||||
|
||||
/* SKU ID structure */
|
||||
typedef struct {
|
||||
int id;
|
||||
const char *name;
|
||||
} sku_info;
|
||||
|
||||
/* Check if the device has a 360 sensor board present */
|
||||
int has_360_sensor_board(void);
|
||||
|
||||
#endif /* __BASEBOARD_VARIANTS_H__ */
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <boardid.h>
|
||||
#include <ec/google/wilco/commands.h>
|
||||
#include <smbios.h>
|
||||
#include <variant/variant.h>
|
||||
|
||||
static uint32_t get_sku_index(void)
|
||||
{
|
||||
return ((!has_360_sensor_board()) | (wilco_ec_signed_fw() << 1));
|
||||
}
|
||||
|
||||
uint32_t sku_id(void)
|
||||
{
|
||||
return skus[get_sku_index()].id;
|
||||
}
|
||||
|
||||
const char *smbios_system_sku(void)
|
||||
{
|
||||
return skus[get_sku_index()].name;
|
||||
}
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
bootblock-y += gpio.c
|
||||
ramstage-y += gpio.c
|
||||
romstage-y += memory.c
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
|
||||
};
|
||||
|
||||
const struct pad_config *variant_override_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* A23 : GPP_A23 ==> RECOVERY# */
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
/* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
/* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
/* C22 : GPP_C22 ==> H1_FLASH_WP */
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
/* C23 : GPP_C23 ==> H1_PCH_INT# */
|
||||
PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT),
|
||||
/* E3 : GPP_E3 ==> MEM_INTERLEAVED */
|
||||
PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
|
||||
/* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
/* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
/* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
/* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
/* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
/* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */
|
||||
PAD_CFG_GPO(GPP_F16, 0, DEEP),
|
||||
/* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
/* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
/* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/* GPD3: GPD3 ==> SIO_PWRBTN# */
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __VARIANT_EC_H__
|
||||
#define __VARIANT_EC_H__
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
/* eSPI virtual wire reporting */
|
||||
#define EC_SCI_GPI GPE0_ESPI
|
||||
|
||||
#endif
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
/* Copied from baseboard and may need to change for the new variant. */
|
||||
|
||||
#endif
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_H
|
||||
#define VARIANT_H
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
const static sku_info skus[] = {
|
||||
/* Deltan 360 - invalid configuration */
|
||||
{ .id = -1, .name = "sku_invalid" },
|
||||
/* Deltan */
|
||||
{ .id = 1, .name = "sku1" },
|
||||
/* Deltan 360 signed - invalid configuration */
|
||||
{ .id = -1, .name = "sku_invalid" },
|
||||
/* Deltan signed */
|
||||
{ .id = 2, .name = "sku2" },
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <string.h>
|
||||
|
||||
static const struct mb_cfg baseboard_memcfg = {
|
||||
.type = MEM_TYPE_DDR4,
|
||||
|
||||
/* DQ byte map */
|
||||
.ddr4_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */
|
||||
.dq1 = { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */
|
||||
.dq2 = { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */
|
||||
.dq3 = { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */
|
||||
.dq4 = { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */
|
||||
.dq5 = { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */
|
||||
.dq6 = { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */
|
||||
.dq7 = { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */
|
||||
},
|
||||
|
||||
.ddr1 = {
|
||||
.dq0 = { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */
|
||||
.dq1 = { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */
|
||||
.dq2 = { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */
|
||||
.dq3 = { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */
|
||||
.dq4 = { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */
|
||||
.dq5 = { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */
|
||||
.dq6 = { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */
|
||||
.dq7 = { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */
|
||||
},
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.ddr4_dqs_map = {
|
||||
.ddr0 = {
|
||||
.dqs0 = 1,
|
||||
.dqs1 = 0,
|
||||
.dqs2 = 1,
|
||||
.dqs3 = 0,
|
||||
.dqs4 = 0,
|
||||
.dqs5 = 1,
|
||||
.dqs6 = 1,
|
||||
.dqs7 = 0,
|
||||
},
|
||||
.ddr1 = {
|
||||
.dqs0 = 1,
|
||||
.dqs1 = 0,
|
||||
.dqs2 = 1,
|
||||
.dqs3 = 0,
|
||||
.dqs4 = 1,
|
||||
.dqs5 = 0,
|
||||
.dqs6 = 1,
|
||||
.dqs7 = 0,
|
||||
}
|
||||
},
|
||||
|
||||
.ect = false, /* Disable Early Command Training */
|
||||
};
|
||||
|
||||
void variant_memory_init(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
const bool half_populated = false;
|
||||
struct mb_cfg new_board_cfg_ddr4;
|
||||
|
||||
memcpy(&new_board_cfg_ddr4, &baseboard_memcfg, sizeof(baseboard_memcfg));
|
||||
|
||||
new_board_cfg_ddr4.ddr4_config.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED);
|
||||
|
||||
memcfg_init(mupd, &new_board_cfg_ddr4, &spd_info, half_populated);
|
||||
}
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
chip soc/intel/tigerlake
|
||||
|
||||
# PCIe Port 8 for LAN
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
|
||||
device domain 0 on
|
||||
device pci 1f.6 on end # GbE 0x15FC
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""MLFS0000""
|
||||
register "desc" = ""Melfas Touchscreen""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E1_IRQ)"
|
||||
register "probed" = "1"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)"
|
||||
register "reset_delay_ms" = "10"
|
||||
register "reset_off_delay_ms" = "5"
|
||||
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
|
||||
register "stop_delay_ms" = "10"
|
||||
register "enable_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
|
||||
register "enable_delay_ms" = "55"
|
||||
register "has_power_resource" = "1"
|
||||
register "device_present_gpio" = "GPP_B4"
|
||||
register "device_present_gpio_invert" = "1"
|
||||
device i2c 34 on end
|
||||
end
|
||||
end # I2C #0
|
||||
device pci 15.1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""Cirque Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.wake" = "GPE0_DW1_07"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end # I2C #1
|
||||
end
|
||||
end
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
bootblock-y += gpio.c
|
||||
ramstage-y += gpio.c
|
||||
romstage-y += memory.c
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <gpio.h>
|
||||
#include <variant/variant.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
|
||||
};
|
||||
|
||||
const struct pad_config *variant_override_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
|
||||
};
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* Check if the device has a 360 sensor board present */
|
||||
int has_360_sensor_board(void)
|
||||
{
|
||||
return gpio_get(SENSOR_DET_360) == 0;
|
||||
}
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __VARIANT_EC_H__
|
||||
#define __VARIANT_EC_H__
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
/* eSPI virtual wire reporting */
|
||||
#define EC_SCI_GPI GPE0_ESPI
|
||||
|
||||
#endif
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
/* Copied from baseboard and may need to change for the new variant. */
|
||||
|
||||
#endif
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_H
|
||||
#define VARIANT_H
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
/* TODO b/153027724: Sensor detection pin */
|
||||
#define SENSOR_DET_360 GPP_C10
|
||||
|
||||
const static sku_info skus[] = {
|
||||
/* Deltaur 360 */
|
||||
{ .id = 1, .name = "sku1" },
|
||||
/* Deltaur */
|
||||
{ .id = 2, .name = "sku2" },
|
||||
/* Deltaur 360 signed */
|
||||
{ .id = 3, .name = "sku3" },
|
||||
/* Deltaur signed */
|
||||
{ .id = 4, .name = "sku4" },
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static const struct mb_cfg baseboard_memcfg = {
|
||||
.type = MEM_TYPE_LP4X,
|
||||
|
||||
/* DQ byte map */
|
||||
.lp4x_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */
|
||||
.dq1 = { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */
|
||||
.dq1 = { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */
|
||||
.dq1 = { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */
|
||||
.dq1 = { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */
|
||||
},
|
||||
.ddr4 = {
|
||||
.dq0 = { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */
|
||||
.dq1 = { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */
|
||||
},
|
||||
.ddr5 = {
|
||||
.dq0 = { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */
|
||||
.dq1 = { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */
|
||||
},
|
||||
.ddr6 = {
|
||||
.dq0 = { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */
|
||||
.dq1 = { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */
|
||||
},
|
||||
.ddr7 = {
|
||||
.dq0 = { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */
|
||||
.dq1 = { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */
|
||||
},
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.lp4x_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */
|
||||
.ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */
|
||||
.ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */
|
||||
.ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */
|
||||
.ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */
|
||||
.ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */
|
||||
.ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */
|
||||
},
|
||||
|
||||
.ect = false, /* Early Command Training */
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &baseboard_memcfg;
|
||||
}
|
||||
|
||||
static int variant_memory_sku(void)
|
||||
{
|
||||
gpio_t spd_gpios[] = {
|
||||
GPIO_MEM_CONFIG_0,
|
||||
GPIO_MEM_CONFIG_1,
|
||||
GPIO_MEM_CONFIG_2,
|
||||
GPIO_MEM_CONFIG_3,
|
||||
GPIO_MEM_CONFIG_4,
|
||||
};
|
||||
|
||||
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
}
|
||||
|
||||
void variant_memory_init(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg *board_cfg = variant_memory_params();
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_MEMORY_DOWN,
|
||||
.cbfs_index = variant_memory_sku(),
|
||||
};
|
||||
const bool half_populated = false;
|
||||
memcfg_init(mupd, board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
chip soc/intel/tigerlake
|
||||
|
||||
device domain 0 on
|
||||
end
|
||||
|
||||
end
|
||||
Loading…
Reference in New Issue