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mb/google/zork: update USB 3 controller phy Parameter for dirinboz 

Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.

BUG=b:175192931
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. run U3 SI/ESD pin test => pass

Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Kevin Chiu 2021-02-04 19:56:41 +08:00 committed by Martin Roth
parent 9a6fc577d1
commit da996f893d
1 changed files with 21 additions and 0 deletions
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21
src/mainboard/google/zork/variants/dirinboz/overridetree.cb
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@ -60,6 +60,27 @@ chip soc/amd/picasso
.tx_res_tune = 0x01,
}"
# USB3 phy parameter
register "usb3_phy_override" = "1"
# USB3 Port0 Default
register "usb3_phy_tune_params[0]" = "{
.rx_eq_delta_iq_ovrd_val = 0x8,
.rx_eq_delta_iq_ovrd_en = 0x1,
}"
# SUP_DIG_LVL_OVRD_IN Default
register "usb3_rx_vref_ctrl" = "0x10"
register "usb3_rx_vref_ctrl_en" = "0x00"
register "usb_3_tx_vboost_lvl" = "0x07"
register "usb_3_tx_vboost_lvl_en" = "0x01"
# SUPX_DIG_LVL_OVRD_IN Default
register "usb_3_rx_vref_ctrl_x" = "0x10"
register "usb_3_rx_vref_ctrl_en_x" = "0x00"
register "usb_3_tx_vboost_lvl_x" = "0x07"
register "usb_3_tx_vboost_lvl_en_x" = "0x01"
# I2C2 for touchscreen and trackpad
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,