t132: Add mmu support

Add support for mmu initialization and enabling caches. mmu_operations provides
functions to add mmap_regions using memrange library and then calls mmu_init for
armv8.

BUG=chrome-os-partner:30688
BRANCH=None
TEST=Compiles rush successfully and boots until depthcharge load. Goes past
all the earlier alignment errors.

Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208762
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b
Reviewed-on: http://review.coreboot.org/8647
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/nvidia/tegra132/Kconfig

@@ -75,6 +75,14 @@ config RAMSTAGE_STACK_BOTTOM
 	hex
 	default 0x8001c000
 
+config TTB_BUFFER
+	hex
+	default 0x80020000
+
+config TTB_SIZE
+	hex
+	default 0x110000
+
 config CBFS_CACHE_ADDRESS
 	hex "memory address to put CBFS cache data"
 	default 0x40006000

src/soc/nvidia/tegra132/Makefile.inc

@@ -50,6 +50,7 @@ ramstage-y += ../tegra/gpio.c
 ramstage-y += ../tegra/i2c.c
 ramstage-y += ../tegra/pinmux.c
 ramstage-y += ramstage.c
+ramstage-y += mmu_operations.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/

src/soc/nvidia/tegra132/mmu_operations.c

@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <memrange.h>
+
+#include <cbmem.h>
+#include <console/console.h>
+
+#include <arch/mmu.h>
+#include "mmu_operations.h"
+#include <soc/addressmap.h>
+
+/* This structure keeps track of all the mmap memory ranges for t132 */
+static struct memranges t132_mmap_ranges;
+
+static void print_memranges(struct memranges *mmap_ranges)
+{
+	struct range_entry *mmap_entry;
+
+	printk(BIOS_DEBUG,"printing mmap entries\n");
+
+	memranges_each_entry(mmap_entry, mmap_ranges) {
+		printk(BIOS_DEBUG,"0x%p 0x%p 0x%lx\n",
+		       (void*)mmap_entry->begin,(void*)mmap_entry->end,mmap_entry->tag);
+	}
+
+}
+
+static void tegra132_memrange_init(void)
+{
+	uint64_t start,end;
+
+	memranges_init_empty(&t132_mmap_ranges);
+
+	memory_in_range_below_4gb(&start,&end);
+
+	/* Device memory below DRAM */
+	memranges_insert(&t132_mmap_ranges, 0, start * MiB, MA_DEV | MA_NS |
+			 MA_RW);
+
+	/* DRAM */
+	memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB,
+			 MA_MEM | MA_NS | MA_RW);
+
+	memory_in_range_above_4gb(&start,&end);
+
+	memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB,
+			 MA_MEM | MA_NS | MA_RW);
+
+	/* SRAM */
+	memranges_insert(&t132_mmap_ranges, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE,
+			 MA_MEM | MA_NS | MA_RW);
+
+	print_memranges(&t132_mmap_ranges);
+}
+
+void tegra132_mmu_init(void)
+{
+	uint64_t *ttb_buffer = (uint64_t*)CONFIG_TTB_BUFFER;
+	uint64_t ttb_size = (uint64_t)CONFIG_TTB_SIZE;
+	tegra132_memrange_init();
+	mmu_init(&t132_mmap_ranges,ttb_buffer,ttb_size);
+	mmu_enable((uint64_t)ttb_buffer);
+}

src/soc/nvidia/tegra132/mmu_operations.h

@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__
+#define __SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__
+
+void tegra132_mmu_init(void);
+
+#endif //__SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__

src/soc/nvidia/tegra132/ramstage.c

@@ -21,6 +21,7 @@
 #include <arch/stages.h>
 #include <soc/addressmap.h>
 #include "mc.h"
+#include "mmu_operations.h"
 
 void arm64_soc_init(void)
 {
@@ -44,4 +45,6 @@ void arm64_soc_init(void)
 	end -= tz_size_mib;
 	write32(end << 20, &mc->security_cfg0);
 	write32(tz_size_mib, &mc->security_cfg1);
+
+	tegra132_mmu_init();
 }