soc/amd/stoneyridge: factor out AOAC offset defines
Factoring out those defines brings the Stoneyridge SoC code a bit more in line with the Cezanne and Picasso SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_STONEYRIDGE_AOAC_DEFS_H
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#define AMD_STONEYRIDGE_AOAC_DEFS_H
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/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
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#define FCH_AOAC_DEV_CLK_GEN 0
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#define FCH_AOAC_DEV_I2C0 5
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#define FCH_AOAC_DEV_I2C1 6
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#define FCH_AOAC_DEV_I2C2 7
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#define FCH_AOAC_DEV_I2C3 8
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#define FCH_AOAC_DEV_UART0 11
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#define FCH_AOAC_DEV_UART1 12
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#define FCH_AOAC_DEV_AMBA 17
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#define FCH_AOAC_DEV_USB2 18
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#define FCH_AOAC_DEV_USB3 23
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#endif /* AMD_STONEYRIDGE_AOAC_DEFS_H */
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@ -131,18 +131,6 @@
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#define DEBUG_PORT_ENABLE BIT(18)
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#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18))
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/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
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#define FCH_AOAC_DEV_CLK_GEN 0
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#define FCH_AOAC_DEV_I2C0 5
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#define FCH_AOAC_DEV_I2C1 6
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#define FCH_AOAC_DEV_I2C2 7
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#define FCH_AOAC_DEV_I2C3 8
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#define FCH_AOAC_DEV_UART0 11
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#define FCH_AOAC_DEV_UART1 12
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#define FCH_AOAC_DEV_AMBA 17
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#define FCH_AOAC_DEV_USB2 18
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#define FCH_AOAC_DEV_USB3 23
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#define PM1_LIMIT 16
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#define GPE0_LIMIT 28
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#define TOTAL_BITS(a) (8 * sizeof(a))
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@ -27,6 +27,7 @@
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#include <soc/pci_devs.h>
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#include <agesa_headers.h>
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#include <soc/acpi.h>
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#include <soc/aoac_defs.h>
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#include <soc/lpc.h>
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#include <soc/nvs.h>
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#include <types.h>
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