soc/amd/stoneyridge: factor out AOAC offset defines

Factoring out those defines brings the Stoneyridge SoC code a bit more
in line with the Cezanne and Picasso SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-06-16 18:46:00 +02:00
parent 8bca2b18bc
commit dac1f66c6c
3 changed files with 19 additions and 12 deletions

View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef AMD_STONEYRIDGE_AOAC_DEFS_H
#define AMD_STONEYRIDGE_AOAC_DEFS_H
/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
#define FCH_AOAC_DEV_CLK_GEN 0
#define FCH_AOAC_DEV_I2C0 5
#define FCH_AOAC_DEV_I2C1 6
#define FCH_AOAC_DEV_I2C2 7
#define FCH_AOAC_DEV_I2C3 8
#define FCH_AOAC_DEV_UART0 11
#define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_USB2 18
#define FCH_AOAC_DEV_USB3 23
#endif /* AMD_STONEYRIDGE_AOAC_DEFS_H */

View File

@ -131,18 +131,6 @@
#define DEBUG_PORT_ENABLE BIT(18)
#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18))
/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
#define FCH_AOAC_DEV_CLK_GEN 0
#define FCH_AOAC_DEV_I2C0 5
#define FCH_AOAC_DEV_I2C1 6
#define FCH_AOAC_DEV_I2C2 7
#define FCH_AOAC_DEV_I2C3 8
#define FCH_AOAC_DEV_UART0 11
#define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_USB2 18
#define FCH_AOAC_DEV_USB3 23
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
#define TOTAL_BITS(a) (8 * sizeof(a))

View File

@ -27,6 +27,7 @@
#include <soc/pci_devs.h>
#include <agesa_headers.h>
#include <soc/acpi.h>
#include <soc/aoac_defs.h>
#include <soc/lpc.h>
#include <soc/nvs.h>
#include <types.h>