soc/mediatek/mt8192: Keep CONN MCU in reset state

Keep the CONN MCU in reset state to prevent CONN from asserting the
clk26m request to SPM.

TEST=clk26m request from conn has been released.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/mt8192/include/soc/pll.h

@@ -306,6 +306,9 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
 DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
 DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
 
+DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24)
+DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12)
+
 enum {
 	INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18),
 	INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18),

src/soc/mediatek/mt8192/pll.c

@@ -10,6 +10,7 @@
 #include <soc/infracfg.h>
 #include <soc/mcucfg.h>
 #include <soc/pll.h>
+#include <soc/wdt.h>
 
 enum mux_id {
 	TOP_AXI_SEL,
@@ -467,6 +468,11 @@ void mt_pll_init(void)
 
 	/* enable [14] dramc_pll104m_ck */
 	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
+
+	/* reset CONNSYS MCU */
+	SET32_BITFIELDS(&mtk_wdt->wdt_swsysrst,
+			WDT_SWSYSRST_KEY, 0x88,
+			WDT_SWSYSRST_CONN_MCU, 0x1);
 }
 
 void mt_pll_raise_little_cpu_freq(u32 freq)