google/oak: Initialize DRAM
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I3ed8bad1bdc7d17e334e0136f92a51c8e7ba4e67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6 Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292692 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13106 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Peter Kao
Patrick Georgi
parent
da1e02a3a0
commit
dac533725c
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@ -22,7 +22,7 @@ verstage-y += chromeos.c
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verstage-y += memlayout.ld
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romstage-y += chromeos.c
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romstage-y += romstage.c
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romstage-y += romstage.c sdram_configs.c
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romstage-y += memlayout.ld
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romstage-y += boardid.c
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@ -19,6 +19,7 @@
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#include <arch/mmu.h>
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#include <cbfs.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <delay.h>
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#include <program_loading.h>
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@ -26,6 +27,7 @@
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#include <symbols.h>
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#include <timestamp.h>
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#include <soc/emi.h>
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#include <soc/mmu_operations.h>
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#include <soc/rtc.h>
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@ -39,7 +41,13 @@ void main(void)
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rtc_boot();
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/* init memory */
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mt_mem_init(get_sdram_config());
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mt8173_mmu_after_dram();
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/* should be called after memory init */
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cbmem_initialize_empty();
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run_ramstage();
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}
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@ -0,0 +1,49 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boardid.h>
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#include <console/console.h>
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#include <soc/emi.h>
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#include <stdlib.h>
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static const struct mt8173_sdram_params sdram_configs[] = {
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#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0000 */
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#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0001 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
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};
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const struct mt8173_sdram_params *get_sdram_config(void)
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{
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u32 ramcode = ram_code();
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if (ramcode >= ARRAY_SIZE(sdram_configs)
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|| sdram_configs[ramcode].type == TYPE_INVALID)
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die("Invalid RAMCODE.");
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return &sdram_configs[ramcode];
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}
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@ -0,0 +1,116 @@
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{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
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{
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.impedance_drvp = 0x9,
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.impedance_drvn = 0xa,
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.datlat_ucfirst = 19,
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.ca_train = {
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[CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2},
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[CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3}
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},
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.ca_train_center = {
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[CHANNEL_A] = 2,
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[CHANNEL_B] = 0
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},
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.wr_level = {
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[CHANNEL_A] = { 5, 6, 5, 6},
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[CHANNEL_B] = { 6, 6, 6, 4}
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},
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.gating_win = {
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[CHANNEL_A] = {
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{ 28, 56},
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{ 0, 0}
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},
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[CHANNEL_B] = {
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{ 28, 56},
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{ 0, 0}
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}
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},
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.rx_dqs_dly = {
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[CHANNEL_A] = 0x110e0b0b,
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[CHANNEL_B] = 0x12100d0d
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},
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.rx_dq_dly = {
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[CHANNEL_A] = {
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0x01040302,
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0x04010300,
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0x02040300,
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0x04030302,
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0x04070400,
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0x07070707,
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0x05070808,
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0x00010404
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},
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[CHANNEL_B] = {
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0x05060604,
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0x04010400,
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0x05070300,
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0x05030504,
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0x07090500,
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0x08090707,
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0x080a0a0a,
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0x02000604
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}
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},
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},
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{
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.actim = 0xaafd478c,
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.actim1 = 0x91001f59,
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.actim05t = 0x000025e1,
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.conf1 = 0x00048403,
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.conf2 = 0x030000a9,
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.ddr2ctl = 0x000063b1,
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.gddr3ctl1 = 0x11000000,
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.misctl0 = 0x21000000,
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.pd_ctrl = 0xd1976442,
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.rkcfg = 0x002156c0,
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.test2_3 = 0xbfc70401,
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.test2_4 = 0x2801110d
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},
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{
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.cona = 0x20102017,
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.conb = 0x17283544,
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.conc = 0x0a1a0b1a,
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.cond = 0x00000000,
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.cone = 0xffff0848,
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.conf = 0x08420000,
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.cong = 0x2b2b2a38,
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.conh = 0x00000000,
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.conm_1 = 0x40000500,
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.conm_2 = 0x400005ff,
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.mdct_1 = 0x80030303,
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.mdct_2 = 0x34220c3f,
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.test0 = 0xcccccccc,
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.test1 = 0xcccccccc,
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.testb = 0x00060124,
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.testc = 0x38470000,
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.testd = 0x00000000,
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.arba = 0x7f077a49,
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.arbc = 0xa0a070dd,
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.arbd = 0x07007046,
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.arbe = 0x40407046,
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.arbf = 0xa0a070c6,
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.arbg = 0xffff7047,
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.arbi = 0x20406188,
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.arbj = 0x9719595e,
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.arbk = 0x64f3fc79,
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.slct_1 = 0x00010800,
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.slct_2 = 0xff03ff00,
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.bmen = 0x00ff0001
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},
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{
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.mrs_1 = 0x00830001,
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.mrs_2 = 0x001c0002,
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.mrs_3 = 0x00010003,
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.mrs_10 = 0x00ff000a,
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.mrs_11 = 0x0000000b,
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.mrs_63 = 0x0000003f
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},
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.type = TYPE_LPDDR3,
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.dram_freq = 896 * MHz,
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},
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@ -0,0 +1,116 @@
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{ /* 2GB (8Gb + 8Gb) for dual rank dram setting */
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{
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.impedance_drvp = 0x9,
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.impedance_drvn = 0xa,
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.datlat_ucfirst = 18,
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.ca_train = {
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[CHANNEL_A] = { 6, 4, 3, 5, 4, 0, 0, 0, 0, 0},
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[CHANNEL_B] = { 1, 1, 1, 1, 0, 6, 5, 5, 5, 7}
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},
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.ca_train_center = {
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[CHANNEL_A] = 3,
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[CHANNEL_B] = 3
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},
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.wr_level = {
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[CHANNEL_A] = { 8, 10, 6, 8},
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[CHANNEL_B] = { 9, 9, 7, 6}
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},
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.gating_win = {
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[CHANNEL_A] = {
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{ 27, 64},
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{ 27, 72}
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},
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[CHANNEL_B] = {
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{ 27, 72},
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{ 27, 72}
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}
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},
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.rx_dqs_dly = {
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[CHANNEL_A] = 0x08080908,
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[CHANNEL_B] = 0x0b0b060b
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},
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.rx_dq_dly = {
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[CHANNEL_A] = {
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0x01010300,
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0x06030002,
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0x01010201,
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0x03020002,
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0x00010103,
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0x02010201,
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0x02040200,
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0x02020201
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},
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[CHANNEL_B] = {
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0x00020202,
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0x02020202,
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0x01020201,
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0x01010100,
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0x01010101,
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0x01000002,
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0x02000201,
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0x00010101,
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}
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},
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},
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{
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.actim = 0xaafd478c,
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.actim1 = 0x91001f59,
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.actim05t = 0x000025e1,
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.conf1 = 0x00048403,
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.conf2 = 0x030000a9,
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.ddr2ctl = 0x000063b1,
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.gddr3ctl1 = 0x11000000,
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.misctl0 = 0x21000000,
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.pd_ctrl = 0xd1976442,
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.rkcfg = 0x002156c1,
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.test2_3 = 0xbfc70401,
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.test2_4 = 0x2801110d
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},
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{
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.cona = 0x50535057,
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.conb = 0x17283544,
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.conc = 0x0a1a0b1a,
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.cond = 0x00000000,
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.cone = 0xffff0848,
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.conf = 0x08420000,
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.cong = 0x2b2b2a38,
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.conh = 0x00000000,
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.conm_1 = 0x40000500,
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.conm_2 = 0x400005ff,
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.mdct_1 = 0x80030303,
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.mdct_2 = 0x34220c3f,
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.test0 = 0xcccccccc,
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.test1 = 0xcccccccc,
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.testb = 0x00060124,
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.testc = 0x38470000,
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.testd = 0x00000000,
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.arba = 0x7f077a49,
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.arbc = 0xa0a070dd,
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.arbd = 0x07007046,
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.arbe = 0x40407046,
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.arbf = 0xa0a070c6,
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.arbg = 0xffff7047,
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.arbi = 0x20406188,
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.arbj = 0x9719595e,
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.arbk = 0x64f3fc79,
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.slct_1 = 0x00010800,
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.slct_2 = 0xff03ff00,
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.bmen = 0x00ff0001
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},
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{
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.mrs_1 = 0x00830001,
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.mrs_2 = 0x001c0002,
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.mrs_3 = 0x00010003,
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.mrs_10 = 0x00ff000a,
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.mrs_11 = 0x0000000b,
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.mrs_63 = 0x0000003f
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},
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.type = TYPE_LPDDR3,
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.dram_freq = 896 * MHz,
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},
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@ -0,0 +1,3 @@
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{
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.type = TYPE_INVALID,
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},
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