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mb/google/brya/var/felwinter: Correct _PLD values 

This patch is to denote the correct value of ACPI _PLD for USB ports.

   +----------------+
   |                |
   |     Screen     |
   |                |
   +----------------+
C2 |                | C1
   | MLB         DB | A0
   |                |
   +----------------+

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ie4f96e3636a8b519923fdba7f9bd07d7a3e1d7ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Won Chung 2022-05-23 22:38:13 +00:00 committed by Martin L Roth
parent fa2e94487c
commit dad64e515b
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/brya/variants/felwinter/overridetree.cb
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@ -341,7 +341,7 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port2 on end
end
chip drivers/usb/acpi
@ -361,7 +361,7 @@ chip soc/intel/alderlake
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
@ -380,7 +380,7 @@ chip soc/intel/alderlake
register "desc" = ""USB2 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
@ -394,7 +394,7 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
device ref usb3_port1 on end
end
end