soc/intel: convert XTAL frequency constant to Kconfig

This converts the constant for the XTAL frequency to a Kconfig option.

Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/alderlake/Kconfig

@@ -136,6 +136,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 120
 
+config CPU_XTAL_HZ
+	default 38400000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133

src/soc/intel/alderlake/cpu.c

@@ -111,15 +111,17 @@ static void configure_dca_cap(void)
 
 static void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);

src/soc/intel/alderlake/include/soc/cpu.h

@@ -19,7 +19,4 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ	38400000
-
 #endif

src/soc/intel/apollolake/Kconfig

@@ -157,6 +157,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 100
 
+config CPU_XTAL_HZ
+	default 19200000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133

src/soc/intel/apollolake/include/soc/cpu.h

@@ -6,9 +6,6 @@
 #include <cpu/x86/msr.h>
 #include <intelblocks/msr.h>
 
-/* Common Timer Copy (CTC) frequency - 19.2MHz. */
-#define CTC_FREQ		19200000
-
 struct device;
 void apollolake_init_cpus(struct device *dev);
 void mainboard_devtree_update(struct device *dev);

src/soc/intel/apollolake/pmutil.c

@@ -180,15 +180,17 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
 
 void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 *    (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
 	wrmsr(MSR_EMULATE_PM_TIMER, msr);

src/soc/intel/cannonlake/Kconfig

@@ -245,6 +245,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 120
 
+config CPU_XTAL_HZ
+	default 24000000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 216

src/soc/intel/cannonlake/cpu.c

@@ -114,19 +114,22 @@ static void enable_pm_timer_emulation(void)
 {
 	msr_t msr;
 
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 *    (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
 	wrmsr(MSR_EMULATE_PM_TIMER, msr);
 }
 
+
 static void set_energy_perf_bias(u8 policy)
 {
 	msr_t msr;

src/soc/intel/cannonlake/include/soc/cpu.h

@@ -22,9 +22,6 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 24MHz. */
-#define CTC_FREQ		24000000
-
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \

src/soc/intel/common/block/cpu/Kconfig

@@ -99,6 +99,11 @@ config INTEL_TME
 	 it would get enabled. If CPU supports MKTME, this same config option
 	 enables MKTME.
 
+config CPU_XTAL_HZ
+	int
+	help
+	  Base clock which virtually everything runs on.
+
 config CPU_SUPPORTS_PM_TIMER_EMULATION
 	bool
 	default n

src/soc/intel/elkhartlake/Kconfig

@@ -133,6 +133,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 120
 
+config CPU_XTAL_HZ
+	default 38400000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133

src/soc/intel/elkhartlake/cpu.c

@@ -105,15 +105,17 @@ static void configure_dca_cap(void)
 
 static void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);

src/soc/intel/elkhartlake/include/soc/cpu.h

@@ -21,9 +21,6 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ	38400000
-
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \

src/soc/intel/icelake/Kconfig

@@ -127,6 +127,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 120
 
+config CPU_XTAL_HZ
+	default 38400000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133

src/soc/intel/icelake/cpu.c

@@ -105,15 +105,17 @@ static void configure_dca_cap(void)
 
 static void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);

src/soc/intel/icelake/include/soc/cpu.h

@@ -21,9 +21,6 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ	38400000
-
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \

src/soc/intel/jasperlake/Kconfig

@@ -137,6 +137,9 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133
 
+config CPU_XTAL_HZ
+	default 38400000
+
 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 	int
 	default 3

src/soc/intel/jasperlake/cpu.c

@@ -105,15 +105,17 @@ static void configure_dca_cap(void)
 
 static void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);

src/soc/intel/jasperlake/include/soc/cpu.h

@@ -21,9 +21,6 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ	38400000
-
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \

src/soc/intel/skylake/Kconfig

@@ -241,6 +241,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 120
 
+config CPU_XTAL_HZ
+	default 24000000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ

src/soc/intel/skylake/cpu.c

@@ -169,15 +169,17 @@ static void configure_c_states(void)
  */
 static void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 *    (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);

src/soc/intel/skylake/include/soc/cpu.h

@@ -25,9 +25,6 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 24MHz. */
-#define CTC_FREQ		24000000
-
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \

src/soc/intel/tigerlake/Kconfig

@@ -138,6 +138,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 120
 
+config CPU_XTAL_HZ
+	default 38400000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133

src/soc/intel/tigerlake/cpu.c

@@ -111,15 +111,17 @@ static void configure_dca_cap(void)
 
 static void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);

src/soc/intel/tigerlake/include/soc/cpu.h

@@ -21,7 +21,4 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ	38400000
-
 #endif